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steve_av
Voyager
Voyager
8,482 Views
Registered: ‎10-06-2015

MIG into another project - vhdl - vivado 2015.4

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I have two project; one a filter the other a mig design.  I want to put the mig design into the filter design but at the moment neither module will have really any common signals except for clock.  My physical hardware only has one clock input.  When I built my mig project, the mig tools asks what the I/Os are for all the physical ddr pins and clock, etc.  When I take that design and put instantiate it into my filter design I'm having some difficulty with the single clock.

 

Is the correct way to use the mig IP with only one clock on your board to use the UI for all your clocking in your design.  I'd have to feed the UI clock to another MMCM which is part of my filter design.

 

These are the critical warnings I'm receiving:

CRITICAL WARNING: [Shape Builder 18-119] Failed to create I/OLOGIC Route Through shape for instance UM/U2/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk. Found overlapping instances within the shape: U3/inst/clkin1_ibufgds and UM/U2/u_mig_7series_0_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk.

 

I can't tie both my MMCMs to the clock input as the tools don't allow that.

 

 

 

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vemulad
Xilinx Employee
Xilinx Employee
16,279 Views
Registered: ‎09-20-2012

Hi @steve_av

 

It looks like you have a single clock port which is going to MIG as well as some other logic in the design. This resulting in two IO buffers inserted.

 

In this case you can select the "no buffer" option for system clock in MIG. Later you can instantiate a differential IO buffer IBUFGDS in top level module and drive its output to both MIG and other logic.

 

Capture.PNG

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
16,280 Views
Registered: ‎09-20-2012

Hi @steve_av

 

It looks like you have a single clock port which is going to MIG as well as some other logic in the design. This resulting in two IO buffers inserted.

 

In this case you can select the "no buffer" option for system clock in MIG. Later you can instantiate a differential IO buffer IBUFGDS in top level module and drive its output to both MIG and other logic.

 

Capture.PNG

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

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vemulad
Xilinx Employee
Xilinx Employee
8,459 Views
Registered: ‎09-20-2012

Hi @steve_av

 

It is recommended not to drive MIG sys_clk input from other MMCM/PLL, refer to this AR http://www.xilinx.com/support/answers/40603.html

 

In case if you are driving MIG sys_clk and other PLL/MMCM from the same clock port then you can use CLOCK_DEDICATED_ROUTE as backbone.

Thanks,
Deepika.
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yenigal
Xilinx Employee
Xilinx Employee
8,449 Views
Registered: ‎02-06-2013

Hi

 

You can also use the flow in below AR to generate extra clocks from the MIG PLL which you can use in the filter design directly instead of using another MMCM.

http://www.xilinx.com/support/answers/43876.html

 

 

Regards,

Satish

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