I have generated a MIG (7 series) core for Cypress CY7C2665KV18 QDRII+ RAM. In the example design project of the core, I added the simulation model of CY7C2665KV18. Everything is ok in the behavioral simulation and the signal init_calib_complete is asserted as shown in the below picture.
But there is a problem in the post-synthesis functional simulation which prevents init_calib_complete be asserted. It seems the problem is in the falling edge of read and write signals (qdriip_w_n and qdriip_r_n).The snapshot of simulation and this strange fault is shown below.
This problem also occurs in the post-implementation simulation.