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spman2
Visitor
Visitor
6,574 Views
Registered: ‎01-01-2013

MIG post-synthesis simulation problem

Hi,

I have generated a MIG (7 series) core for Cypress CY7C2665KV18 QDRII+ RAM. In the example design project of the core, I added the simulation model of CY7C2665KV18. Everything is ok in the behavioral simulation and the signal init_calib_complete is asserted as shown in the below picture.

Behavioral.JPG

But there is a problem in the post-synthesis functional simulation which prevents init_calib_complete be asserted. It seems the problem is in the falling edge of read and write signals (qdriip_w_n and qdriip_r_n).The snapshot of simulation and this strange fault is shown below.

Post_Synth_Functional.JPG

Post_Synth_Functional_Zoom.JPG

This problem also occurs in the post-implementation simulation.

Could anyone please help me?

Thanks in advance

 

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yenigal
Xilinx Employee
Xilinx Employee
6,569 Views
Registered: ‎02-06-2013

Hi

 

Mig supports only Behavioral simulaiton.

 

Post synthesis and post implementation simulation are not supported.

Regards,

Satish

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