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Adventurer
Adventurer
169 Views
Registered: ‎03-29-2008

MIG seven series SYS_CLK no buffer

The Vivado 2019.1 MIG 4.2 for seven series tool allows the selection of sys_clk as "NO_BUFFER" when making DDR3 interfaces. I would like to use this option in a design to minimize input clocks. However, I also note that sys_clk must be "low jitter", under what circumstances can I use the "NO_BUFFER" option?


I am looking for allowed frequencies and jitter. How do I determine those numbers? I see no guidance on the topic in UG586. Did I miss something?


Thank You
Nick

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Xilinx Employee
Xilinx Employee
128 Views
Registered: ‎08-21-2007

回复: MIG seven series SYS_CLK no buffer

The system clock goes into the MMCM inside the MIG IP. You can refer to the 7 Series datasheet for the input jitter requiment. For the input frequency, you can choose it within MIG IP wizard.

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