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Adventurer
Adventurer
695 Views
Registered: ‎03-28-2014

MIG version registers have empty values

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I'm getting the following error in Vivado 2018.3 on my current build and I'm not sure what happened because everything had been working just fine. Nothing related to the MIG has changed between a build that didn't produce this critical warning and the one that now does produce it.

 

 [Xicom 50-46] One or more detected MIG version registers have empty values: MIG properties will not be built.
Parameter Map Version: 0, Error Map Version: 0, Calibration Map Version: 0, Warning Map Version: 0

According to AR64923 this issue was resolved in Vivado 2016.3 so I'm not quite sure what to do. I've tried regenerating the output products for the MIG with no luck.

I just tried to regenerate the MIG again and I got the following critical warning:

 [Memdata 28-203] ADDRESS_SPACE or ADDRESS_MAP tag name path/to/ip/DDR4_SDRAM was not found. Some data may have not been translated.
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Xilinx Employee
Xilinx Employee
625 Views
Registered: ‎08-21-2007

回复: MIG version registers have empty values

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Can you have a try with IP example design after you regerenerated the MIG core? Please also check the system clock input and system reset. Make sure there's a active-high reset pulse after the system clock input has been stable.

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4 Replies
Xilinx Employee
Xilinx Employee
664 Views
Registered: ‎05-08-2012

Re: MIG version registers have empty values

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Hi @dcwhitehead 

Is the project available to send either as an attachment, or via private message? This appears to be a generation problem with the IP. Usually regenerating the IP would be the first suggestion, but it appears this did not work.

Alternatives would be to archive, and unarchive the project, or recreating the IP to see if these resolve the problem.


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Xilinx Employee
Xilinx Employee
626 Views
Registered: ‎08-21-2007

回复: MIG version registers have empty values

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Can you have a try with IP example design after you regerenerated the MIG core? Please also check the system clock input and system reset. Make sure there's a active-high reset pulse after the system clock input has been stable.

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Adventurer
Adventurer
602 Views
Registered: ‎03-28-2014

回复: MIG version registers have empty values

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@krenand @marcb, thanks for the help.

It turns out I had changed the input clock for the MMCM I was using to generate to the reset from an external oscillator to an output clock from the RF Data Converters IP block and for some reason that clock is not active.

Is software required to bring up the output clocks from the RF Data Converters? I had been expecting them to initialized based on the IP settings without further interaction.

 

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Xilinx Employee
Xilinx Employee
591 Views
Registered: ‎08-21-2007

回复: MIG version registers have empty values

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I suggest you create a new topic for the "RF Data Converters".

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