07-12-2017 12:47 PM
When using MIG, and setting my clock frequency to the maximum value (400MHz), I get a message in yellow saying:
"To achieve optimum resource utilization, maintain default clock period given by the tool or a value greater than default clock period. Please contact Xilinx Technical Support for further information".
If I understand correctly, that means that if I reduce the clock frequency, it will use less FPGA resources. Is that all it means?
07-12-2017 02:33 PM
I take it that the MIG IP/core/tool was created/optimized for certain DDR based interfaces and moving away from those parameters would cost additional penalties in device resources. The higher you go the more resources are consumed to implement the interface. Above ~333MHz it will be more likely that more resources are consumed. I believe this is a message that usually only occurs when using MIG without cost optimized portfolio devices like Spartan-7 or Artix-7. You can generate the core and example designs to see how much additional resources it expects to consume at different frequencies to get an idea of how much additional resources it will consume.
08-04-2017 03:08 PM
That messaging will be updated in future versions of Vivado to make it more clear exactly what's going on. Overall there was an effort to improve the MIG resource utilization for some smaller devices and product families and it's not only the default clock period that's optimized it's all of the settings on that page of the MIG configuration tool. Once the default settings are changed the resource utilization jumps. You can implement some example designs yourself to see how much utilization increases from the default configuration.