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kimsclub007
Observer
Observer
8,095 Views
Registered: ‎06-03-2014

MIG7 DDR3 PHY initialization

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I attached pdf file which includes waveform image.

The images shows read some data without write operation prior to read during initialization sequence.

It looks garbage value is read from the memory.

 

I am going to use MIG phy with my own memory model.

There are appropriate function which is for counter-code between MIG PHY and Micron memory model because it operates through pre-determined sequence, but it could be different from my model.

I am considering skipping some init sequence of MIG phy or modifying my model according to the MIG phy init sequence.

 

My quenstion is about read operation without write operation prior to read.

Is Micron ddr3 model support to output garbage data if there is a read request when memoy is not initialized?

I am wondering, why those read operation are needed, and what is the exact function of that sequences.

 

I showed the time when those reads occurs.

I am inspecting Initialization sequence with simulation(MIG IP+Micron ddr3 model) under example design. 

Command sequence progresses like below after reset 

 

  1. Reset
  2. MRS setting (2-3-1-0)
  3. ZQCL
  4. ACT
  5. READ
  6. Precharge
  7. Refresh (iteration)
  8. ACT
  9. READ

10. Precharge all refresh

11. MRS setting(1) for write leveling

12. …

 

There are READ commands(5, 9) after ZQCL(init_state == phase lock) and Refresh(init_state == dqsfound)

The below data is read despite there was no write prior to read

 

 

0xc5755fa59e391384

0xa67078e1bb00effe

.

.

.

 

I checked MRS setting because I doubted thouse data is from MPR, but it is not set for MPR read.

Please let me know how the data is read.

 

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criley
Xilinx Employee
Xilinx Employee
13,977 Views
Registered: ‎08-16-2007

Yes, the micron model supports reads before the memory has been initialized. The only problem is the read data will be unknown (garbage).

 

You didn't indicate which FPGA device family you are targeting but the first reads after the MIG initialization and calibration sequence has completed are part of the "Periodic Read" logic which is required for dynamic calibration. During a Periodic Read the phase alignment of DQS can be dynamically adjusted and is a required part of the MIG controller in order to ensure capturing read data reliably over PVT variation.

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1 Reply
criley
Xilinx Employee
Xilinx Employee
13,978 Views
Registered: ‎08-16-2007

Yes, the micron model supports reads before the memory has been initialized. The only problem is the read data will be unknown (garbage).

 

You didn't indicate which FPGA device family you are targeting but the first reads after the MIG initialization and calibration sequence has completed are part of the "Periodic Read" logic which is required for dynamic calibration. During a Periodic Read the phase alignment of DQS can be dynamically adjusted and is a required part of the MIG controller in order to ensure capturing read data reliably over PVT variation.

View solution in original post