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csavarese
Visitor
Visitor
7,896 Views
Registered: ‎09-30-2011

MIG7 DDR3 S_AXI_WREADY help?

Hi all,

I have a design that was working just fine, and suddenly I'm having issues with S_AXI_WREADY on the MIG7 core that I can't seem to resolve.  I even rolled my environment back, and still can't seem to fix it.  Can anyone please help me figure out what I've done wrong?

 

The attached screenshot shows several successful writes from my custom AXI4 master to the Xilinx IP MIG7 core.  Then on the last attempt, where much more data is being written, the IP core deasserts S_AXI_WREADY after just a few words.  My master obediantly waits, but S_AXI_WREADY never comes back.  I can't puzzle out why it's being deasserted.  Any ideas would be greatly appreciated!  Thanks!

mig7_s_axi_wready.jpg
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driesd
Xilinx Employee
Xilinx Employee
7,882 Views
Registered: ‎11-28-2007

Hi,

 

looks all fine to me from this side, except for the fact that WREADY does not get asserted anymore.

Is this waveform for the AXI slave side (MIG)?

 

MIG is possibly a special case: it can take quite a while before the IP finishes calibration, so possibly the MIG AXI buffer is now full.

Can you do a read? (that would also confirm the MIG has finished calibration)

 

 

Best regards

Dries

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