MIG7 setting unmatched on AC701

[JohnsonHu]

Hi,

I'm trying to re-target a design  from KC705 to AC701.

The MIG7 of KC705 works fine.

Thanks for the pdf file, xtp225_ac701_ming-c-2015, which has step-by-step setting statement of the MIG7. 

    DDR Clock period= 2500ps (400MHz)

    PLL input clock (CLKIN) =50000ps (200MHz)

however, after the MIG7 is configured and generated, CLKIN turns to be 100MHz (not as expected)?! 

Please help that if it's the limit of Artix or AC701?

Johnson 2020-11-03

[JohnsonHu]

Hi,

Here are some captures about my question:

1) MIG7 is configured based on the document: xtp225-ac701-mig-c-2015-1.pdf

2) Setting Input Clock as 200MHz during the step-by-step setting

3) the generated MIG whose SYS_CLK is 100MHz instead of 200MHz ?!

Please teach me what's going wrong ?

Johnson

[kren]

Please check the preriod constraint on the sys_clk and check if it's 5ns.

[JohnsonHu]

Hi Kren:

The only constrain (selection) of sys_clk is at the configuration path. 

Anyway, the report shows what was set as below. 

*****************************************

Vivado Project Options:
Target Device : xc7a200t-fbg676
Speed Grade : -2
HDL : verilog
Synthesis Tool : VIVADO

/*******************************************************/
/* Controller 0 */
/*******************************************************/
Controller Options :
Memory : DDR3_SDRAM
Interface : AXI
Design Clock Frequency : 2500 ps ( 0.00 MHz)
Phy to Controller Clock Ratio : 4:1
Input Clock Period : 5000 ps
CLKFBOUT_MULT (PLL) : 4
DIVCLK_DIVIDE (PLL) : 1
VCC_AUX IO : 1.8V
Memory Type : SODIMMs
Memory Part : MT8JTF12864HZ-1G6

*************************************************************

Input Clock Period=5000 ps or 5ns, which implies 200MHz, right ?

Johnson

[kren]

Please check it in the top .xdc file.