cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
454 Views
Registered: ‎05-25-2018

MIG7 unexpected behavior on custom board Kintex7

Jump to solution

Hello,

I designed a telecommunication purpose custom Kintex 7 board. Everything works fine expect the SO-DIMM DDR3 interface.

I used the Vivado MIG to generate the interface with the following parameters:

Vivado Project Options:

Target Device : xc7k160t-ffg676

Speed Grade : -2

HDL : vhdl

Synthesis Tool : VIVADO

MIG Output Options:

Module Name : mig_7series_0

No of Controllers : 1

FPGA Options:

System Clock Type : Differential

Reference Clock Type : Use System Clock

Debug Port : ON

Internal Vref : disabled

IO Power Reduction : OFF

XADC instantiation in MIG : Enabled

 

Extended FPGA Options:

DCI for DQ,DQS/DQS#,DM : enabled

Internal Termination (HR Banks) : 50 Ohms

 

/*******************************************************/

/* Controller 0 */

/*******************************************************/

Controller Options :

Memory : DDR3_SDRAM

Interface : NATIVE

Design Clock Frequency : 2500 ps (400.00 MHz)

Phy to Controller Clock Ratio : 4:1

Input Clock Period : 5000 ps

CLKFBOUT_MULT (PLL) : 4

DIVCLK_DIVIDE (PLL) : 1

VCC_AUX IO : 1.8V

Memory Type : SODIMMs

Memory Part : MT8KTF51264HZ-1G9

Equivalent Part(s) : --

Data Width : 64

ECC : Disabled

Data Mask : disabled

ORDERING : Strict

 

AXI Parameters :

Data Width : 512

Arbitration Scheme : RD_PRI_REG

Narrow Burst Support : 0

ID Width : 4

 

Memory Options:

Burst Length (MR0[1:0]) : 8 - Fixed

Read Burst Type (MR0[3]) : Sequential

CAS Latency (MR0[6:4]) : 6

Output Drive Strength (MR1[5,1]) : RZQ/6

Controller CS option : Enable

Rtt_NOM - ODT (MR1[9,6,2]) : RZQ/6

Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off

Memory Address Mapping : ROW_BANK_COLUMN

Bank Selections:

System_Clock:

SignalName: sys_clk_p/n

PadLocation: AA10/AB10(CC_P/N) Bank: 33

System_Control:

SignalName: sys_rst

PadLocation: D25(DQS) Bank: 14

SignalName: init_calib_complete

PadLocation: D15 Bank: 15

SignalName: tg_compare_error

PadLocation: G26 Bank: 14

 

Module: MT8KTF51264HZ-1G9P1

Oscilattor: SI545 200MHz

The traces were routed with 50 Ohm impedance because its only a 6 layer board.

VRN/VRP Resistor: 100Ohm

In the ILA I get the following signals:

(The forum didnt let me post the exported ILA)

dqsfound_start = 1 dqsfound_err = 1

rdlvl_start = 0 rdlvl_done = 10

oclkdelay_calib_start = 0 oclkdelay_calib_done = 1

The data and read offset didnt count at all.

As far as i understand I shouldnt get this combination of signals. I started with probeing the power supplies and the DQS signals on the so-dimm module. The 1.5V, 0.75V had noise below 30mVpp. The signal integrity was similar all across on the strobes i could probe (Sorry for the image quality).

I have no idea how to continue debuging of the interface. Could you help me in the debuging?

Bests,
Balázs

 

DQS_SI.PNG
fail_dqs2.PNG
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
429 Views
Registered: ‎08-21-2007

You can refer to "Debugging PHASER_IN DQSFOUND Calibration Failures" section in ug586.

View solution in original post

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
430 Views
Registered: ‎08-21-2007

You can refer to "Debugging PHASER_IN DQSFOUND Calibration Failures" section in ug586.

View solution in original post

0 Kudos