cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
1keith1
Participant
Participant
5,525 Views
Registered: ‎02-17-2014

MPMC - Adding Chip Selects Doesn't Increase Size

Jump to solution

I'm using the MPMC for a Virtex 5.

 

The Memory I'm using has two chips, with 2 chip selects and one Clock enable to both.

 

each chip has:

 

3 Bank bits (8)

15 Row bits (32k)

10 Column bits (1k)

8 bit Data width

 

So each chip has 8*32k*1k*8bits = 256m * 8bits =256MB

 

I have a total of 512MB therefore, however the MPMC GUI says I have 256MB.

 

The tool is not factoring in that I have 2 chip selects, allowing me to have 2 x 256MB.

 

Here's what I have in the GUI:

GUI1.PNG

GUI2.PNG

 

0 Kudos
1 Solution

Accepted Solutions
gszakacs
Professor
Professor
10,308 Views
Registered: ‎08-14-2007

In your screen shot I see "No. of Ranks" set to 1.  This means that the tools are generating two chip selects but they are identical - either both on or both off.  You need to set No. of Ranks to 2 to let the tools know there are two sets of chips, and then you should see 512MB.

-- Gabor

View solution in original post

3 Replies
gszakacs
Professor
Professor
10,309 Views
Registered: ‎08-14-2007

In your screen shot I see "No. of Ranks" set to 1.  This means that the tools are generating two chip selects but they are identical - either both on or both off.  You need to set No. of Ranks to 2 to let the tools know there are two sets of chips, and then you should see 512MB.

-- Gabor

View solution in original post

1keith1
Participant
Participant
5,506 Views
Registered: ‎02-17-2014

I thought this might be the case... 

I read on wikipedia that a memory rank is "is a set of DRAM chips connected to the same chip select" but I see that I misunderstood it.

 

I noticed ranks is limited to 2, I'm curious how you would implement a memory like this:

Capture.PNG

This would have 4 ranks correct?

 

Fortunately I am only implementing the CS0,CS1 of the above memory, so it doesn't concern me. (Turns out we didn't include the two ball's corresponding to CS2,CS3 on the board) 

0 Kudos
gszakacs
Professor
Professor
5,502 Views
Registered: ‎08-14-2007

Extending memory to more ranks is not difficult in terms of the logic, however it becomes hard from a signal integrity standpoint, since you are now connecting each DQ and DQS line to four loads.  It's likely that the Xilinx MIG core that underlies the MPMC was limited to 2 ranks because that was the most that could work reliably at reasonable speeds given the drive strength of the Virtex 5 I/O pins.  You might be able to find third party IP for controlling more memory, but that would be tough to integrate with an embedded processor system.  You could also check if moving to DDR3 allows you to select more ranks, but I seem to recall that it is also limited to 2.

-- Gabor