[Memory Core Error]

[joel.sanchez]

Hi,

I'm doing the implementation of my design using Vivado and I don't know how to solve that error:

[Mig 66-99] Memory Core Error - [memory/ddr/u_ddr4_0] Either port(s) c0_sys_clk_p, c0_sys_clk_n is/are not placed or un-supported clocking structure/circuit for memory ip instance. Please refer to clocking section of PG150 for supported clocking structures. 

[Mig 66-99] Memory Core Error - [memory/ddr/u_ddr4_0] Port(s) c0_ddr4_ck_c[0],c0_ddr4_ck_t[0],c0_ddr4_adr[0],c0_ddr4_adr[1],c0_ddr4_adr[2],c0_ddr4_adr[3],c0_ddr4_adr[4],c0_ddr4_adr[5],c0_ddr4_adr[6],c0_ddr4_adr[7],c0_ddr4_adr[8],c0_ddr4_adr[9],c0_ddr4_adr[10],c0_ddr4_adr[11],c0_ddr4_adr[12],c0_ddr4_adr[13],c0_ddr4_adr[14],c0_ddr4_adr[15],c0_ddr4_adr[16],c0_ddr4_ba[0],c0_ddr4_ba[1],c0_ddr4_bg[0],c0_sys_clk_n,c0_sys_clk_p,c0_ddr4_bg[1],c0_ddr4_cs_n[0],c0_ddr4_cke[0],c0_ddr4_odt[0],c0_ddr4_act_n,c0_ddr4_reset_n,c0_ddr4_dqs_c[0],c0_ddr4_dqs_t[0],c0_ddr4_dm_dbi_n[0],c0_ddr4_dq[0],c0_ddr4_dq[1],c0_ddr4_dq[2],c0_ddr4_dq[3],c0_ddr4_dq[4],c0_ddr4_dq[5],c0_ddr4_dq[6],c0_ddr4_dq[7],c0_ddr4_dqs_c[2],c0_ddr4_dqs_t[2],c0_ddr4_dm_dbi_n[2],c0_ddr4_dq[16],c0_ddr4_dq[17],c0_ddr4_dq[18],c0_ddr4_dq[19],c0_ddr4_dq[20],c0_ddr4_dq[21],c0_ddr4_dq[22],c0_ddr4_dq[23],c0_ddr4_dqs_c[3],c0_ddr4_dqs_t[3],c0_ddr4_dm_dbi_n[3],c0_ddr4_dq[24],c0_ddr4_dq[25],c0_ddr4_dq[26],c0_ddr4_dq[27],c0_ddr4_dq[28],c0_ddr4_dq[29],c0_ddr4_dq[30],c0_ddr4_dq[31],c0_ddr4_dqs_c[4],c0_ddr4_dqs_t[4],c0_ddr4_dm_dbi_n[4],c0_ddr4_dq[32],c0_ddr4_dq[33],c0_ddr4_dq[34],c0_ddr4_dq[35],c0_ddr4_dq[36],c0_ddr4_dq[37],c0_ddr4_dq[38],c0_ddr4_dq[39],c0_ddr4_dqs_c[5],c0_ddr4_dqs_t[5],c0_ddr4_dm_dbi_n[5],c0_ddr4_dq[40],c0_ddr4_dq[41],c0_ddr4_dq[42],c0_ddr4_dq[43],c0_ddr4_dq[44],c0_ddr4_dq[45],c0_ddr4_dq[46],c0_ddr4_dq[47],c0_ddr4_dqs_c[6],c0_ddr4_dqs_t[6],c0_ddr4_dm_dbi_n[6],c0_ddr4_dq[48],c0_ddr4_dq[49],c0_ddr4_dq[50],c0_ddr4_dq[51],c0_ddr4_dq[52],c0_ddr4_dq[53],c0_ddr4_dq[54],c0_ddr4_dq[55],c0_ddr4_dqs_c[7],c0_ddr4_dqs_t[7],c0_ddr4_dm_dbi_n[7],c0_ddr4_dq[56],c0_ddr4_dq[57],c0_ddr4_dq[58],c0_ddr4_dq[59],c0_ddr4_dq[60],c0_ddr4_dq[61],c0_ddr4_dq[62],c0_ddr4_dq[63],c0_ddr4_dqs_c[1],c0_ddr4_dqs_t[1],c0_ddr4_dm_dbi_n[1],c0_ddr4_dq[8],c0_ddr4_dq[9],c0_ddr4_dq[10],c0_ddr4_dq[11],c0_ddr4_dq[12],c0_ddr4_dq[13],c0_ddr4_dq[14],c0_ddr4_dq[15] is/are not placed. Assign all ports to valid sites. 

I generated the block using Vivado IP Catalog and I didn't touch anything, what should I do?

Thanks.

[jmcclusk]

You need to assign those two pins to a differential input clock pair.   Check your board schematic and find where these reference clocks are located, then create PACKAGE_PIN property assignments for them in your XDC..    Or load the synthesized netlist into Vivado, and open the "IO Pin" window,  then use the pulldown menu to assign these pins to the right place.

[joel.sanchez]

Hi @jmcclusk,

I understand what you're saying that I should assign those pins to the fpga, but when I have created all the IP Blocks that my design need (bram, xdma, ddr4,...) an XDC file is auto-generated for everyone and this files have the physical pins assigned.

For example the ddr4 IP block has an XDC file that have some lines like:

create_clock -period 13.501 [get_ports c0_sys_clk_p]

set_property OUTPUT_IMPEDANCE RDRV_40_40 [ get_ports "c0_ddr4_dqs_c[4]" ]

Aren't those the pins needed? When yoy say "load the synthesized netlist into Vivado" are those pins that I wrote above? How should I use that XDC?

Thanks.

Regards,

Joel

[jmcclusk]

Yes, it's true that the DDR memory controller will pretty much assign all the pins, although I understand that this has changed with the latest DDR4 controller.    But the system clock input for the DDR controller is still manually assigned, because it can go on a fair number of different clock capable inputs.   

To do final pin assignment in Vivado, it's pretty easy..    First "Run Synthesis", and then "Open Synthesized Design".   Then go to the Window tab and open the "IO Pin" window,  which will show all the top level IO pins on the design.    Go down the list and find ALL the pins which don't have an assignment, and then assign them to the right place..     I'm not saying this is trivial, but every pin needs to be assigned in order to generate a bitstream.    Once the pins are all assigned, hit the "Save" icon (top left, looks like a floppy disk), and it will save the pin assignments to the active XDC target file.    Then you can proceed to Implementation.

[joel.sanchez]

Hi @jmcclusk,

sorry for replying late but I was with hard work and couldn't do so much. Thanks for all the process you explained, I found the IO Pins windows and it's true that clock and reset don't have the correct package assigned. I have been searching the schematic for my fpga (vup9) and i found this file:

https://www.xilinx.com/support/packagefiles/usapackages/xcvu9pflgb2104pkg.txt

As you can see there are all the pins and packages but I don't know what I should choose because no one of them have the same name as used in the IP Block. Should I look for a specific "IO Type" value or something like that?


Thanks

[jmcclusk]

The package file is only useful during the PCB design phase.   If you have a board already built, you have to consult the board schematic (or user guide) to see what input pins have a differential clock.    If you are doing a proof of concept build, then you should choose a pair of clock capable inputs that are close to your DDRx memory bank.   They should definitely be in the same half (upper or lower) as your memory.

[joel.sanchez]

Hi @jmcclusk,

the only document I have been able to find is:

https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf

I'm doing a search using my fpga reference that is FLGB2104 VU9P. I will continue searching.


Thanks

[joel.sanchez]

Hi @jmcclusk,

sorry for the issues but I'm new with Vivado and once I know how to do it with those pins I will be able to do it with every design. I will attache an image which I think it's the schematic ( I haven't been able to find any more schematic of my fpga). Vivado put two of the pins that I need on the AF43 and AF38, so for my clk and reset can I use any of the empty pins in the image?

Thanks and sorry again

PS. The image can also be viewed on page 290 of https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf

[joel.sanchez]

Hi @jmcclusk,

this post in an update. I have the following contents inside the XDC file :

#############################################################################################################
create_clock -name sys_clk -period 10 [get_ports sys_clk_p]
#
#############################################################################################################
set_false_path -from [get_ports sys_rst_n]
set_property PULLUP true [get_ports sys_rst_n]
set_property IOSTANDARD LVCMOS18 [get_ports sys_rst_n]
set_property PACKAGE_PIN AR26 [get_ports sys_rst_n]
#
set_property CONFIG_VOLTAGE 1.8 [current_design]
#
#############################################################################################################
set_property PACKAGE_PIN AH39 [get_ports sys_clk_n]
set_property PACKAGE_PIN AH38 [get_ports sys_clk_p]

The Synthesis and implementation goes fine but when I generate the bitstream an error occurs:

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: sys_clk_n, and sys_clk_p.

Looking through the process I find a warning on implementation:

[Vivado 12-1411] Cannot set LOC property of ports, Could not find a valid bel for the shape with the following elements: 
pcie_module/refclk_ibuf
sys_clk_n
sys_clk_p

This warning is because I use IBUFDS_GTE4, I readed that this can be a problem, but this is used by XDMA example so I don't know how really works and if it can be changed.

I would appreciate some help. Thanks.

Regards,

Joel

[jmcclusk · Accepted solution]

Oh!  The IBUFDS_GTE4 can ONLY be connected to the GTY (or GTH) reference clock inputs,  nowhere else.   It needs to be connected on the Quad where your PCIe GT elements are located,  or at least adjacent.   If you have an 8 lane PCIe, then connect it to one of the two quads.

[joel.sanchez]

Hi @jmcclusk,

I will try it. Thank you!!

Regards,

Joel