cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
maju42
Adventurer
Adventurer
1,008 Views
Registered: ‎05-31-2019

Memory block ram in Vivado

Jump to solution

Hey all,

I have created a simple dummy module as follows in Vivado 2019.1.

 

module dummyexample

  #(parameter DATA_WIDTH=7,
    parameter ADDR_WIDTH=22)
    (
     input [(DATA_WIDTH-1):0] data_in,
     input [(ADDR_WIDTH-1):0] extramem_addr,
     input clk,
     output [(DATA_WIDTH-1):0] data_out
     );

   (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
   (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram2[2**ADDR_WIDTH-1:0];
   reg [ADDR_WIDTH-1:0] read_addr_reg;
   
   always @ (posedge clk) begin
      read_addr_reg <= extramem_addr; 
      ram[extramem_addr] <= data_in;
   end

   assign data_out = ram[read_addr_reg];
   
endmodule

 

I am instantiating this from another top module and sending in some wires as follows:

wire[7:0] dummywire_in;
wire[7:0] dummywire_addr; 
wire[7:0] dummywire_out;

dummyexample senddata(
    .clk(clk),
    .data_in(dummywire_in),
    .extramem_addr(dummywire_addr),
    .data_out(dummywire_out)
);

I am not sending in any actual data because I just want to see the memory overhead of declaring the array in my 'dummyexample' module. I was hoping to see some changes in the Overhead utilization of the Synthesis reports after declaring those two memory arrays. But the result remains the same as it was before creating this module. I am not seeing any changes in LUTRAM or BRAM report after synthesis. Is there any solution how to fix this and get the synthesis to actually read those two arrays?

0 Kudos
1 Solution

Accepted Solutions
necare81
Explorer
Explorer
917 Views
Registered: ‎03-31-2016

That would fit in a single block RAM.  Any device should have multiple block RAMs but now many depend on which device,  for instance a large Virtex Utlrascale will have a couple thousand but a small Spartan 6 might have only 10s.  The tools are capable of cascading them to make them deeper and/or ganging them together to make them wider

The original question, at least as I read it, was how much of that could be considered overhead. 

That you can figure out from the datasheets very easily by looking at the modes for a blockram.  They should be listed as something like 36(32 +4 parity)x512 ,18x1K...etc.  If your desired width and depth matches those exactly you have no wasted space.  If you needed 513 entries of 37 bits each you would be wasting a lot.

View solution in original post

5 Replies
necare81
Explorer
Explorer
957 Views
Registered: ‎03-31-2016

First you do not call a module, you create an instance of it.

Second your top level instance of the dummyexample "sendata" does not match the port list of the definition of dummyexample so it should have given you syntax errors.

Third, synthesis tools are very good at optimization so just having dummy wires that don't go anywhere are going to be optimized away.  If a modules inputs have no connections to external pins or the outputs never reach output pins they will be optimized away.

Fourth, your posted code has only one memory array so your core question doesn't really make much sense.

Fifth your code declares a 4MB RAM that is going to be hard to fit in almost all devices.

0 Kudos
maju42
Adventurer
Adventurer
952 Views
Registered: ‎05-31-2019

Sorry for the confusion, I edited the code posted.

0 Kudos
necare81
Explorer
Explorer
934 Views
Registered: ‎03-31-2016

The new code looks like it should at least compile but the other points apply.

Your new code never uses ram2 so the optimization routines will discard it very quickly.

It is not clear what you are really trying to achieve, the two ram instances are identical.  The "overhead" will be determined by the width and depth of the memory you are trying to create.  For example a 32-bit entry by 512 location memory you will perfectly map to a single block ram or you could do a 31-bit entry with 512 locations and have 1-bit per entry because that is the closest supported block ram mode.

0 Kudos
maju42
Adventurer
Adventurer
929 Views
Registered: ‎05-31-2019

So you are suggesting to declare the ram instance as:

reg[32-1:0] ram[512-1:0] , otherwise it will be too big for the on-chip ram in FPGA. Is that correct?

0 Kudos
necare81
Explorer
Explorer
918 Views
Registered: ‎03-31-2016

That would fit in a single block RAM.  Any device should have multiple block RAMs but now many depend on which device,  for instance a large Virtex Utlrascale will have a couple thousand but a small Spartan 6 might have only 10s.  The tools are capable of cascading them to make them deeper and/or ganging them together to make them wider

The original question, at least as I read it, was how much of that could be considered overhead. 

That you can figure out from the datasheets very easily by looking at the modes for a blockram.  They should be listed as something like 36(32 +4 parity)x512 ,18x1K...etc.  If your desired width and depth matches those exactly you have no wasted space.  If you needed 513 entries of 37 bits each you would be wasting a lot.

View solution in original post