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dimitris78
Adventurer
Adventurer
676 Views
Registered: ‎09-13-2019

Memory controller implementation error due to non-global sys clock

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I have a DDR4 memory controller on an xcku11p (kintex us) fpga that get's the system clock from an internal net (c0_sys_clk_i) - as opposed to a pair of external differential pins.

Still there are restrictions on the c0_sys_clk_i net and one of them is that it needs a global clock input. 

However due an error in board design, the available clock comes in through a non-GC pin. The memory controller therefore produces this error:

[Mig 66-99] Memory Core Error - [u_x_rob_ddr4] System Clock ports must be assigned to a global clock (GC) pin pair. c0_sys_clk_p is assigned to Site AU12, with pad function IO_L2P_T0L_N2_FOE_B_65, which is not a GC pin.

What are my options ? Is there a way to route the non-GC pin to the clock network ? Is there a way to downgrade the error so that the implementation completes ?

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kshimizu
Xilinx Employee
Xilinx Employee
643 Views
Registered: ‎03-04-2018

Hello @dimitris78 ,

 

Please use the differential clock connected to GCIO as sys_clk.  It is described in the Clocking, page85-86 in PG150.

 

If it is not used the GCIO, there is no work-around at this time

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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GCIO.PNG
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kshimizu
Xilinx Employee
Xilinx Employee
644 Views
Registered: ‎03-04-2018

Hello @dimitris78 ,

 

Please use the differential clock connected to GCIO as sys_clk.  It is described in the Clocking, page85-86 in PG150.

 

If it is not used the GCIO, there is no work-around at this time

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------

View solution in original post

GCIO.PNG
dimitris78
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Registered: ‎09-13-2019

@kshimizu I tried with a global clock (pins AM15 & AN15 on XCKU11P-FFVE1517) and although I'm not getting the MIG failure I get the following placement error when i try to connect though IBUFDS -> IBUFG:

[Place 30-716] Sub-optimal placement for a global clock-capable IO pin-BUFGCE-MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets dev/c_sys_clk] >

dev/inst_bufg_ddr4_clk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y25
dev/include_ddr4_controllers.ddr4_controller_2/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst (MMCME4_ADV.CLKIN1) is locked to MMCM_X0Y6
dev/include_ddr4_controllers.ddr4_controller_1/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst (MMCME4_ADV.CLKIN1) is locked to MMCM_X0Y3

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
dev/include_ddr4_controllers.ddr4_controller_1/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst (MMCME4_ADV.CLKOUT0) is locked to MMCM_X0Y3
dev/include_ddr4_controllers.ddr4_controller_1/inst/u_ddr4_infrastructure/u_bufg_divClk (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y72

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
dev/inst_bufg_ddr4_clk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y25

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
dev/include_ddr4_controllers.ddr4_controller_1/inst/u_ddr4_infrastructure/u_bufg_divClk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y72

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
dev/include_ddr4_controllers.ddr4_controller_1/inst/u_ddr4_infrastructure/u_bufg_riuClk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y95

Clock Rule: rule_gclkio_bufg
Status: PASS
Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
dev/inst_ibufds_user_accessible_clk/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y80
dev/inst_bufg_ddr4_clk (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y25

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: A MMCM driving a BUFG must be placed in the same clock region of the device as the
BUFG
dev/include_ddr4_controllers.ddr4_controller_2/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst (MMCME4_ADV.CLKOUT0) is locked to MMCM_X0Y6
dev/include_ddr4_controllers.ddr4_controller_2/inst/u_ddr4_infrastructure/u_bufg_divClk (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y145

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
dev/include_ddr4_controllers.ddr4_controller_2/inst/u_ddr4_infrastructure/u_bufg_divClk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y145

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
dev/include_ddr4_controllers.ddr4_controller_2/inst/u_ddr4_infrastructure/u_bufg_dbg_clk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y144

Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and dev/include_ddr4_controllers.ddr4_controller_2/inst/u_ddr4_infrastructure/u_bufg_riuClk (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y167

 

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