01-08-2019 09:07 AM
At UG583 (V1.14) TABLE A-4 " DDR4 Address/Command/Control Bus Skew Limit"
the skew values referenced to Address/Command/Control without CK , i.e- the skew between signals inside the group, as it is derating table, are above the value 8(ps). approved skews values are go up to 150 ps on the table.
but according notes on the table:
note 1: This specification is for the address/command/control bus skew only. The separate CK-to-address specification must be met as specified.
2. See Table 2-18 and Table 2-35 for the original specifications associated with this table.
when you look at table 2-18 : address/command/control to CK value is 8(ps).
this mean that the skew between the ck and each of the signals address/command/control shall be less then 8ps, while on the other hand the derating table approve skew of up to 150 ps between the signals,
that is for my understanding contradiction in the requirements,
can you advise to resolve my misunderstanding how i can combine the derating table with the table 2-18 to create the right rule for skew between all signals of the Address/Command/Control Bus itself and between ck(clock) to the bus Address/Command/Control?
thanks in advance
01-18-2019 09:01 AM
The application here for the CAC bus derating tables is instead of having a skew of 8ps from the min to max signal lengths you can have larger skews depending on your memory component speed, FPGA speed rating, and target operating rate. Table 2-18 shows the expectation that the CK can be no farther away than 8ps from any CAC bus signal, and this is the starting point for the derating tables. Now that you're increasing the CAC bus skews the expectation is that the CK is still no further than Xps away from any CAC bus signal. Here I would take the average of the CAC bus lengths and use that as your target for the CK.
01-18-2019 11:50 AM
The maximum skew values shown in Tables 2-17 and 2-18 of UG583 presume that you'll be operating an interface at the fastest rate allowed by a controller (FPGA), using the slowest DDR parts that work at that rate.
For example, if you're laying out a DDR4 interface that will be running at 1600 Mbps, and the controller is rated to run at 1600 Mbps and the DDR parts are rated to run at 1600 Mbps, your skews are controlled by Tables 2-17 and 2-18. Note that those values correspond to the dark-gray, normalized boxes in the de-rating tables.
If, instead, you select a controller (i.e., faster Xilinx part) that is rated to run that interface at 1866, but you're only running at 1600--with the same 1600-rated memory parts, your DQ-DQS skew allowance grows from +/- 10 pS to +/- 31 pS.
Likewise, had you stayed with the 1600-rated controller, and still run it at 1600, but used 2133-rated memory parts, that skew allowance would grow to +/- 36 pS.
The same calculations apply when considering C-A-C grouping, using Table A-2.
I hope this makes things clearer.