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vdinesh@igcar.gov.in
Contributor
Contributor
616 Views
Registered: ‎11-05-2019

Memory mapping is failing in xilinx vivado 2019.1

1.I created a project in xilinx vivado 2019.1.

2.To store the data and read back from the memory, for this i used a BRAM controller and AXI block memory generator.

3.After generating bitstream , exported to SDK to check the BRAM. here it is showing 8/16/32 bit failed.

This is the result showing in TeraTerm 

This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
Testing memory region: axi_bram_ctrl_0_Mem0
Memory Controller: axi_bram_ctrl_0
Base Address: 0xc0000000
Size: 0x00010000 bytes
32-bit test: FAILED!
16-bit test: FAILED!
8-bit test: FAILED!
--Memory Test Application Complete--

 

 

 

any suggestions.

Thank you .

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4 Replies
shengjie
Moderator
Moderator
605 Views
Registered: ‎06-30-2019

Hi vdinesh@igcar.gov.in ,

 

Can you share a screenshot of Block Design and Address Editor?

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vdinesh@igcar.gov.in
Contributor
Contributor
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Registered: ‎11-05-2019

 
block diagram.png
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shengjie
Moderator
Moderator
505 Views
Registered: ‎06-30-2019

Hi vdinesh@igcar.gov.in ,

 

Maybe you can assert ILA to the S_AXI interface of BRAM controller, and check data.

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sm7ed
Observer
Observer
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Registered: ‎05-16-2018

Maybe try enabling the cache so that you can connect the BRAM to the M_AXI_DC and M_AXI_IC ports and see if that works. Example:

suggestion.png

 

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