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Adventurer
Adventurer
300 Views
Registered: ‎06-30-2016

Memory signal group assignment

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Hi all,

I have a Vivado project with a XCKU5P-1FFVB676 and four 16bits DDR3 Modules. When it comes to assign the pinout, I've done my first two DDR modules as follow, so the byte 0 group has the DQ0:

temp.png

 

Now, for the other two moduldes, I've done as follow:

temp2.png

Is this OK? As you can see the byte 0 has DQ[24-31] and Address/Ctrl remains the same as the first two modules. Vivado didn't complain. I've done it like this because it would be easier to do the pcb routing.

Thanks in advance.

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Xilinx Employee
Xilinx Employee
271 Views
Registered: ‎08-21-2007

回复: Memory signal group assignment

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The pin assignments are good and you can go ahead with your design.

View solution in original post

1 Reply
Xilinx Employee
Xilinx Employee
272 Views
Registered: ‎08-21-2007

回复: Memory signal group assignment

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The pin assignments are good and you can go ahead with your design.

View solution in original post