cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jhgf
Contributor
Contributor
646 Views
Registered: ‎09-24-2016

Metastability in distributed RAM address

Jump to solution

Hi,

I have a question about the distributed RAM (or memory in general).

 

1) Assume that data is metastable and the write address is metastability-free

I know that if metastability occurs in the data, then an invalid data will be written in the memory location specified by the write address. After a while, the metastability will be resolved, and a valid data can be read from the memory. We can also use synchronizers to give time to the invalid data to be resolved.

 

2) Assume that data is stable but the write address is metastable

but what about metastability in the address? will the data be written in two different address? can synchronizers resolve the issue in this case?

0 Kudos
1 Solution

Accepted Solutions
avrumw
Expert
Expert
435 Views
Registered: ‎01-23-2009

I am pretty sure this is a diagram of what the "Distributed Memory Generator" (an IP wizard) can create, not an actual schematic of the RAM cell itself. 

As far as I know, these input registers are not part of the distributed RAM cell, but may be additional registers (taken from another slice) that can be added to modify the behavior of the core generated by the wizard.

The distributed RAM cells are (and as far as I know, always have been) single clock latency writes (the writes take effect on the rising edge of the write clock) and zero latency reads (the reads are combinatorial from the A and DPRA ports). Since the output of the LUT (which is the RAM cell) can go to the flip-flop located in the same slice, you can (for "free") add a pipeline register to the output, but there are no extra flip-flops available in the slice for registering the inputs; these would have to come from another slice...

Avrum

 

View solution in original post

0 Kudos
4 Replies
631 Views
Registered: ‎01-22-2015

@jhgf 

Metastability leads to unpredictable results.

When writing to RAM, you must ensure that both the address inputs and the data inputs to RAM are stable before you toggle the write-enable input to RAM.

You can remove metastability from data/address lines by using a multibit synchronizer  - or, after asserting data/address lines, wait an appropriate number of clock cycles until metastability has settled out.

Mark

0 Kudos
avrumw
Expert
Expert
611 Views
Registered: ‎01-23-2009

As markg@prosensing.com said, you probably shouldn't do either of these things. The internal structure of the distributed RAMs isn't explicitly stated (it may be available in a Xilinx patent...), and there is no specific documentation as to its metastability characteristics.

I can pretty confidently state that trying to use an unsynchronized address input will result in bad things - you will likely be able to corrupt any one (or even several) bits in a number of different address locations in the RAM with a single write with unsynchronized address inputs.

The best approach is to deal with synchronization and metastability before the RAM using known synchronization techniques.

Avrum

0 Kudos
jhgf
Contributor
Contributor
506 Views
Registered: ‎09-24-2016

Thanks for your answer,

I found the internal architecture of the dual port distributed RAM in DS322 document.

I see that there is an internal register for the address port. Is it true ? I'm using RAM64X1D in my project, is there an internal register for the address port?

 
 

 

Capture.JPG
0 Kudos
avrumw
Expert
Expert
436 Views
Registered: ‎01-23-2009

I am pretty sure this is a diagram of what the "Distributed Memory Generator" (an IP wizard) can create, not an actual schematic of the RAM cell itself. 

As far as I know, these input registers are not part of the distributed RAM cell, but may be additional registers (taken from another slice) that can be added to modify the behavior of the core generated by the wizard.

The distributed RAM cells are (and as far as I know, always have been) single clock latency writes (the writes take effect on the rising edge of the write clock) and zero latency reads (the reads are combinatorial from the A and DPRA ports). Since the output of the LUT (which is the RAM cell) can go to the flip-flop located in the same slice, you can (for "free") add a pipeline register to the output, but there are no extra flip-flops available in the slice for registering the inputs; these would have to come from another slice...

Avrum

 

View solution in original post

0 Kudos