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apogeedbkxilinx
Adventurer
Adventurer
9,705 Views
Registered: ‎04-02-2010

MiG Ultrascale calibration pass but init_calib_complete low

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Tools/etc:

Vivado 2015.2.1_AR65261

Kintex Ultrascale 115 ES2

MiG 7.1 DDR4 controller.

 

Issue:

Looking at the XSDB MIG GUI in Vivado Lab calibration passes (see attached image).  However, the init_calib_complete port of the IP is not high.  Any ideas?

migGui.PNG
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apogeedbkxilinx
Adventurer
Adventurer
17,811 Views
Registered: ‎04-02-2010

Thank you for the replies.  I believe the issue was a failed timing constraint.  On a rebuild of the core that met timing I don't see the issue.

View solution in original post

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4 Replies
balkris
Xilinx Employee
Xilinx Employee
9,694 Views
Registered: ‎08-01-2008
Check this debug Guide

http://www.xilinx.com/Attachment/Xilinx_Answer_60305_rev_2014_4.pdf
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
9,694 Views
Registered: ‎08-01-2008
check this tread as well

https://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/MIG-quot-init-calib-complete-quot-signal-does-not-go-high-during/td-p/375673
Thanks and Regards
Balkrishan
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vsrunga
Xilinx Employee
Xilinx Employee
9,692 Views
Registered: ‎07-11-2011

Hi

 

I suspect if you are capturing correct signal with proper trigger condion.

Can you set trigger condition for rising_edge of init_calib_complete signal, give a push button reset and show us ILA captures and XSDB results ?

You can upload ILA catutes and xsdb(in csv) format 

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apogeedbkxilinx
Adventurer
Adventurer
17,812 Views
Registered: ‎04-02-2010

Thank you for the replies.  I believe the issue was a failed timing constraint.  On a rebuild of the core that met timing I don't see the issue.

View solution in original post

0 Kudos