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jtarantino
Visitor
Visitor
6,944 Views
Registered: ‎11-21-2007

[Mig 66-119] Phy core regeneration & stitching failed Vivado 2016.3

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I am getting the following error using Vivado 2016.3:

 

[Mig 66-119] Phy core regeneration & stitching failed

 

This design was fully operational and tested when compiled using Vivado 2016.2.  I upgraded all IP multiple times to get the upgrade into all levels. Still I get the same error.

 

I am opening this service request as instructed by AR# 67957 where it states:

 

"The PHY IP is required to be updated in each Vivado release. If the full IP cannot be upgraded, please open a Service Request."

 

Details:

Vivado 2013.2 - works

Vivado 2016.3 - error

DDR4 SDRAM (MIG) (2.1) IP

HW-Z1-ZCU102 Evaluation Board (XCZU9EG-FFVB1156)

Device: MT40A256M16GE-075E

 

 

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vemulad
Xilinx Employee
Xilinx Employee
12,065 Views
Registered: ‎09-20-2012

Hi @jtarantino

 

I saw this issue in 2016.3 where the temporary directory created by tool while implementing mig cores had invalid characters in its path. The debug_core_synth.log file should have the error which can explain the reason for the failure.

 

Please try below steps.

 

1.       Open synthesized design and run below command

implement_mig_cores –force –outputdir <path>

Ensure the path mentioned above has only supported characters.

2.       Save the design

3.       Use “Run Implementation” GUI flow.

Thanks,
Deepika.
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8 Replies
vemulad
Xilinx Employee
Xilinx Employee
12,066 Views
Registered: ‎09-20-2012

Hi @jtarantino

 

I saw this issue in 2016.3 where the temporary directory created by tool while implementing mig cores had invalid characters in its path. The debug_core_synth.log file should have the error which can explain the reason for the failure.

 

Please try below steps.

 

1.       Open synthesized design and run below command

implement_mig_cores –force –outputdir <path>

Ensure the path mentioned above has only supported characters.

2.       Save the design

3.       Use “Run Implementation” GUI flow.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

criley
Xilinx Employee
Xilinx Employee
6,937 Views
Registered: ‎08-16-2007

If you are upgrading a design from 2013.2 to 2016.3 then you will definitely need to build a new DDR4 IP from scratch as there were major changes to the IP and Vivado software. I would recommend regenerating the DDR4 IP from scratch anyways as sometimes a problem can occur when migrating/updating the IP such as relative paths in and pointint to speific certain files are no longer valid.

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jtarantino
Visitor
Visitor
6,922 Views
Registered: ‎11-21-2007

Thank you for your quick reply.  I did erase all of the Mig IP and regenerate from scratch.  The problem was the path to the temporary files.

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anilkumarp
Visitor
Visitor
6,540 Views
Registered: ‎09-27-2016

Hi,

I am facing the same problem while using Vivado 16.3. I have deleted the generated memory controller files and regenerated by using Vivado 16.3. But still I am facing the same error. Can you please let me know how this error was fixed for you.

 

Thanks,

Anil

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anilkumarp
Visitor
Visitor
6,508 Views
Registered: ‎09-27-2016

This issue is with the special characters within the path at which the Vivado tool is creating the temporary folder for Phy core regeneration & stitching. I have changed the username with minimum characters so that Vivado is not used any special characters while creating the temporary folder.

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raymond_adeas
Observer
Observer
6,336 Views
Registered: ‎07-14-2016

Hi Deepika,

 

I also have this issue and i tried your suggestion but without success.

When i save the design after running the command 'implement_mig_cores' the synthesized design becomes out of date.

For some reason Vivado wants to re-write my constraints files (target.xdc (ok, fair enough), timing.xdc(why is vivado re-writing this non-target xdc????)).

When I force up-to-date, implementation fails. -> Caught exception:
ERROR: [ProjectBase 2-104] Project name 'C:/Users/HERMAN~1/AppData/Local/Temp/9780/prj_ip_0.xpr' is illegal.

 

When i restart synthesis and implementation, a new temp directory is made again in AppData and i get a similar error.

 

How can i tell Vivado to use a specific temp directory?

 

Thanks,

Raymond

 

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jasonhannon
Visitor
Visitor
5,992 Views
Registered: ‎08-20-2013
Deepika,

I am having the exact same problem as Raymond. Do we have a solution to this yet?
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vemulad
Xilinx Employee
Xilinx Employee
5,977 Views
Registered: ‎09-20-2012

Hi @jasonhannon

 

You can run the below command from vivado tcl console and rerun Implementation.
 
set_param general.legalFilePathCheckRelaxed 1 
 
You can also place this command in init.tcl file.

This issue is fixed in vivado 2016.4.

 

 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)