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Majed_45
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Registered: ‎05-15-2020

Mig ipcore

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Hello everyone. 

At the start my english is not good.

I want to make a my  frist project with mig core in vivado 2019.2 and artix chip  but I don't know how should I start.

Please help me

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Majed_45
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Registered: ‎05-15-2020

Thank you very very much.

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rpr
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Registered: ‎11-09-2017

Hi @Majed_45 

Detailed information is documented in UG586 - MIG configuration, Design guidelines, board routing guidelines. UG586 - 7 Series FPGAs Memory Interface Solution User Guide

Known issues MIG 7-Series - IP Release Notes and Known Issues for Vivado

Maximum Physical Interface (PHY) Rate for Memory Interfaces IP https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf

Regards
Pratap

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Majed_45
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Registered: ‎05-15-2020

Thank you very very much.

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