05-18-2020 08:22 AM
At the start my english is not good.
I want to make a my frist project with mig core in vivado 2019.2 and artix chip but I don't know how should I start.
Please help me
05-18-2020 09:03 PM
Detailed information is documented in UG586 - MIG configuration, Design guidelines, board routing guidelines. UG586 - 7 Series FPGAs Memory Interface Solution User Guide
Maximum Physical Interface (PHY) Rate for Memory Interfaces IP https://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf