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Visitor
Visitor
10,585 Views
Registered: ‎01-02-2013

Mirrored addresses for dual rank DDR3 components

To simplify the PCB design (Zynq and Virtex 7) of a 32 bit DDR3 memory (consisting of two x16 components, one on the top layer, second on the bottom layer) it would be helpful to use the mirrored addresses (similar as used on the DIMM modules: A3<->A4, A5<->A6, A7<->A8, BA0<->BA1). In the UG 586 ("7 Series FPGAs MIS v2.0") there is a description of a "CA_MIRROR" flag, which controlls address mirroring on the second rank of UDIMMs. Is there also a solution for memory components?

 

Thanks, Alexander

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Xilinx Employee
Xilinx Employee
10,578 Views
Registered: ‎07-11-2011

Re: Mirrored addresses for dual rank DDR3 components

Hi,

 

For componnets you have to take care that maximum electrical delays between DDR3 SDRAM signals specified in UG586 are met.

I think MIG enables Mmirror function as DIMM vendor supports it, do you know a component that have mirror capability?

Can you provide the part number?

 

 

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Visitor
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Re: Mirrored addresses for dual rank DDR3 components

Hi Vanitha,

thank you fror your reponse. 

Part number for example is MT41K256M16XX. In general, the DDR3 SDRAMs have no special mirror capability (in contrast to - for example - RLDRAM3 devices). Also UDIMMs are equipped with the same DDR3 components types (for example, see http://www.jedec.org/sites/default/files/docs/design/DDR3/PC3_12800_UDIMM_V07_RC_B0_20070529.zip). 

The mirroring influences the write address to some internal registers of the components ("load mode") and the memory controller must be able to handle the different addresses of the second rank. I am wondering if MIS supports the mirrored adressing also for components and not only for UDIMMs as suggested in the UG586. 

(Of course, electrical delays are also very important, but this is not the problem I have requested...)

 

Thanks, Alexander

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: Mirrored addresses for dual rank DDR3 components

Hi,

 

As far as I know DDR3 SDRAM components do not support mirror function, and hence the controller do not have the feature.

So the reason I asked if you know any DDR3 component that supports mirror capability.

If you find one such component/vendor then contact your FAE, based on your project potential details he will do the needful

Currently MIG has no mirrored adressing for components

 

 

Hope this helps

 

 

Regards,

Vanitha

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Visitor
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Re: Mirrored addresses for dual rank DDR3 components

Hi Vanitha, 

thank you for your replies. 

I know (see my 2nd post), that there is no special mirrored operation mode of DDR3 SDRAMs and there are no special mirrored DDR3 SDRAM types. Nevertheless in UDIMMs the mirrored address schema is used to simplify the PCB layout (and signal integritry), the memory controller has to handle the different address scheme for the second rank. This is only necessary during configuration and calibration. SInce the Xilinx controller already supports the mirrored addressing for UDIMMs (which are equivalent to a few DDR3 components), I wondering if there is also a possibility to use the "CA_MIRROR" flag or a similar workaround for components. There is no magic or extensive engineering effort to implement this feature, its only another wiring scheme. 

 

Thanks, Alexander

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-11-2011

Re: Mirrored addresses for dual rank DDR3 components

Hi,

 

I think I and you were saying the same thing

 

I understood your requirement but unfortunately address mirroring idea for components is not thought and not HW evaluated by Xilinx. It might be simple, but currently there is no proven workaround/solution.

 

 

 

 

 

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