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Visitor
Visitor
942 Views
Registered: ‎06-29-2018

Missing MIG simulation file (SIP_PHY_CONTROL) in compiled library for modelsim

I get the following error when running Modelsim after compiling libraries for a Spartan 7-25.  I am using Vivado 2018.2 and Modelsim 10.2a.  SIP_PHY_CONTROL in instantiated by phy_control.v.

# Loading unisims_ver.PHY_CONTROL
# ** Error: (vsim-3033) C:/Xilinx/Vivado/2018.2/data/verilog/src/unisims/PHY_CONTROL.v(569): Instantiation of 'SIP_PHY_CONTROL' failed. The design unit was not found.
#
# Region: /sim_tb_top/u_ip_top/u_mig_7series_0/u_mig_7series_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0/u_ddr_phy_4lanes/phy_control_i
# Searched libraries:
# C:/Users/user/Data/Technology/Electrical/FPGA/ArtyS7/Proj-25/MIG_25_1/MIG_25_1.sim/sim_1/behav/modelsim/modelsim_lib/msim/xil_defaultlib
# C:/Users/user/Data/Technology/Electrical/FPGA/ArtyS7/Proj-25/MIG_25_1/MIG_25_1.cache/compile_simlib/modelsim/unisims_ver
# C:/Users/user/Data/Technology/Electrical/FPGA/ArtyS7/Proj-25/MIG_25_1/MIG_25_1.cache/compile_simlib/modelsim/unimacro_ver
# C:/Users/user/Data/Technology/Electrical/FPGA/ArtyS7/Proj-25/MIG_25_1/MIG_25_1.cache/compile_simlib/modelsim/secureip
# C:/Users/user/Data/Technology/Electrical/FPGA/ArtyS7/Proj-25/MIG_25_1/MIG_25_1.cache/compile_simlib/modelsim/xpm
# C:/Users/user/Data/Technology/Electrical/FPGA/ArtyS7/Proj-25/MIG_25_1/MIG_25_1.cache/compile_simlib/modelsim/unisims_ver

Can someone please supply this file?

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Xilinx Employee
Xilinx Employee
897 Views
Registered: ‎09-05-2018

Hey @mvogt997,

I think the problem is actually your Modelsim version. Can you install Mentor Graphic ModelSim SE/DE/PE (10.6c)? This is the compatible tool listed on page 13 of UG973 for Vivado 2018.2.

Nicholas Moellers

Xilinx Worldwide Technical Support
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Moderator
Moderator
896 Views
Registered: ‎11-28-2016

Hello @mvogt997

Modelsim 10.2a is an unsupported version for Vivado 2018.2.  Based on UG973 for Vivado 2018.2 the supported version is ModelSim 10.6c.  It's very likely the simulation issues you're seeing are due to this mismatch.  Here's a link to UG973 for Vivado 2018.2:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug973-vivado-release-notes-install-license.pdf

supported_sim_versions.PNG

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Visitor
Visitor
877 Views
Registered: ‎06-29-2018

Thanks for that.

I assume Modelsim 10.6c or later would work, correct?

Mark

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Moderator
Moderator
864 Views
Registered: ‎11-28-2016

Hello @mvogt997,

I wouldn't assume that a later version would work.  These were the tested versions we know work so anything other than that is an unknown.

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Visitor
Visitor
425 Views
Registered: ‎03-05-2018

So you're stating that we cannot simulate a DDR_MIG in the Aldec Active-HDL simulator right now? Will this ever be available? My error states this during the elaboration phase: # ELBREAD: Error: Design unit SIP_PHASER_IN instantiated in simprims_ver.PHASER_IN_PHY not found in searched libraries: simprims_ver, techl.
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