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mrbietola
Scholar
Scholar
6,644 Views
Registered: ‎05-31-2012

Multi controller MIG clock topology

Hi, i have 2 DDR3 controllers in one MIG instance.

Every controller puts out a  c*_ui_clk.   Microblaze Data Cache is connected to an axi interconnect and "sees" both controllers. It's clocked by c0_ui_clk.    

Are the accesses to controller 1 still synchronous?   

If i add a VDMA that writes to controller 1, should it be clocked by c1_ui_clk?    If i use c0_ui_clk instead, the interconnect manage the clock conversion?

 

It's better to clock all the peripherals to only c0_ui_clk (design is easier to implement)?   What about a VDMA that accesses both controllers?

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vsrunga
Xilinx Employee
Xilinx Employee
6,641 Views
Registered: ‎07-11-2011

@mrbietola

 

Even though they are of same frequency(same meory clock and phy to controller ratio)  they are genarted using difefrent MMCMs

 

We recommend you to use respective ui_clk for the AXI interconnect.

 

-Vanitha

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mrbietola
Scholar
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6,621 Views
Registered: ‎05-31-2012

Thank you for your reply, but i'm not sure i understand, can you formulate a connection example?

 

For example 2 VDMAs, each connected to a different controller...

 

Should i use 2 interconnects, each interconnect clocked by C*_ui_clk (ACLK pin),  each VDMA clocked by C*_ui_clk?

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mrbietola
Scholar
Scholar
6,609 Views
Registered: ‎05-31-2012

If i try to do 2 interconnect and run automation, Vivado still to use C0_ui_clk for both interconnects. If the c*_ui_clk are asynchronous, why Vivado try to connect to an asynch clock?

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