05-10-2017 12:12 AM
I'm trying to interface with QDRII+ and I use NetFPGA-1G CML Kintex-7
I have done the simulation, it works just fine, however when I implement to the real board, the calibration is failed.
I have 2 questions:
Thanks in advance.
05-10-2017 12:25 AM
1.Yes the input clock period should be equal to the frequency you have selected during the core generation.
You can change the clock period during clock generation(set to 4000 or 2500 etc) so that you can see option of 5000ps(200Mhz) for input clock period so that you can use your available system clock on the board.
2. When you select 200Mhz for input clock the reference clock provides use system clock option so that it will use the input clock.
05-10-2017 01:45 AM
Check option 1 in below AR which applies to QDRII+ as well
05-10-2017 03:21 AM
It's really helpful for me.
But when I try to implement to real board, calibration is still failed.
I use dbg_phy_status bits to light up a LED, but the result is that all the bit of dbg_phy_status is off. (at least, the bit 0 is off meanning that there are no problems with clock source and rst signal)
What should I do now?
05-10-2017 09:38 PM
After carefully debugging, I found that the Stage 1 read calibration is started but it cannot finish.
Really need your advice.
04-02-2018 01:10 PM
hello,i am a student from China,and i study netfpga-1g-cml recently,can you tell me which software simulation is used about netfpga,and is there other library file or something else need to be download？Thank you very much！