NetFPGA SUME DDR

[pcdeni]

Hi,

I have trouble instantiating a MIG and using the DDR on the NetFPGA SUME board.

In the acceptance test, the init_calib_complete goes high, however I cannot recreat it in vivado 2020.1

The sources my configurations were based on:

NetFPGA SUME live repository's multiple projects

OSNT SUME live repository's extmem project 

Tapasco project.

Additionally as the vc709 is similar, I have taken a look on the followings:

https://www.youtube.com/watch?v=0KnvW_6Bgu0&ab_channel=XilinxInc

https://www.xilinx.com/support/documentation/boards_and_kits/vc709/2014_4/xtp235-vc709-mig-c-2014-4.pdf

https://github.com/Xilinx/HLx_Examples/tree/master/Acceleration/tcp_ip/scripts/VC709/DRAM

However, I have tried multiple configurations and none of them worked.

Could somebody point me into the right direction?

[kshimizu]

Hello　@pcdeni ,

Do you use the 7-series FPGA with DDR3 in vivado2020.1?  If 7-series FPGA is used, please refer to ug586, especially how to create an example design.  It mentions from page.21 in ug586.

https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

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[pcdeni]

Hi Kshimizu,

It didn't help. Please check the reference designs linked in the first post.

However if we are talking about MIG, why is it, that every time I select a controller with 2 DDR3 interfaces for identical SODIMM modules, the data width for C0 gets overwritten to 512, regardless of what was selected before, while C1 is being left alone?

If there are 2 separate MIG controllers instantiated, external XADC is required. Which controller should provide the axi clock for the XADC?