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Registered: ‎04-09-2016

New User DDR3 AXI4 Interface Question

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I'm a new Xilinx user but have some experience with Altera.  I'm porting my Altera design that uses a custom state machine to read/write DDR2 memory on an eval board thru their DDR2 controller IP.  I'm trying to figure out how to interface to the Xilinx MIG DDR3 controller IP.  I apparently must use AXI4, but because my custom design connects to it directly I need to know the signals and functional timing.  Altera provided this info for their DDR controller (after a LOT of digging) but I haven't found this info on Xilinx or ARM websites.  Can someone point me to where this detailed info can be found?  Thanks!

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Registered: ‎04-09-2016

Re: New User DDR3 AXI4 Interface Question

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Yes, that's what I'm looking for.  Thanks pete_128.  I didn't look far enough into UG586 (and didn't expect the user interface to be defined there so didn't look hard enough).  I found a Nov 2015 version of UG586 when I hit the User Manual button in MIG. FYI. I wish the user data width could be specified like Altera allows.  Thanks all.

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Anonymous
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Re: New User DDR3 AXI4 Interface Question

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Hi

 

The good thing about AXI is it is a standard specification. Its not even Xilinx specific. The formal documentation for it is ARM IHI 0022D.  You may need to register for a free ARM account. After that, you just need to build your IP with consideration to this spec.

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Registered: ‎04-09-2016

Re: New User DDR3 AXI4 Interface Question

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Thanks for the ARM doc number.

 

I've found out how to have MIG use its native interface, which leads to 2 more questions:

1.  What Xilinx doc specifies the native interface and shows functional timing?

2.  How do I get the MIG to generate the user data width I want (32 bits).  The Arty board has a 16-bit physical interface, but I don't see how to set the user width.  It always generates a 128-bit interface.

 

Thanks for any info on these questions.

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Xilinx Employee
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Registered: ‎07-11-2011

Re: New User DDR3 AXI4 Interface Question

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@spatterson691

 

1. Which FPGA device and MIG version are you using?

You can refer PG150(Ultrascale), UG586(7 Series), UG086(Virtex 6) 

Links to all MIG related documents can be accessed from here: http://www.xilinx.com/support/answers/34243.html

 

2. MIG  user interface data width is nck_per_clk *memory data width  where nck_per_clk = 4, 2 (depends on the PHY to Controller Clock
ratio chosen in the GUI), other values are not possible

 

Hope this helps

 

-Vanitha

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Re: New User DDR3 AXI4 Interface Question

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Vanitha,  

Thanks for the info.  The Arty board uses an Artix-35T FPGA (xc7a35ticsg324-1L) FPGA.  I'm using MIG on Vivado 2015.4. When I hit the MIG Version Info button, it errors out because it "cannot find Acrobat." However, it brings up UG586 just fine when I hit the User Manual.  The UG586 MIG brings up is a 2015 version (says v2.4 on the title page), which is much newer than the 2011 version I was using.  I'll read this newer version and see if any of my questions are answered.

 

I did not know that the user data width depends on the "Phy to Controller Clock Ratio" (nCK_PER_CLK).  The MIG only allows 4:1 clock ratio in my case, but with a 16-bit physical interface wouldn't that lead to a 64 bit wide user interface, not 128 bits?  I should state that the 128-bit number comes from the stub file MIG creates, which I suppose could be in error(?).  

 

Anyone know where the native MIG user interface spec/functional description can be found?

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Xilinx Employee
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Registered: ‎07-11-2011

Re: New User DDR3 AXI4 Interface Question

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@spatterson691

 

Sorry,  I missed there is a correction here:

 MIG user interface data width is nck_per_clk *memory data width * 2(to account for double data rate)

 

Native interface details can be found in the same UG586

 

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Re: New User DDR3 AXI4 Interface Question

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Thanks.  That explains the data width.  Unfortunate since I want 32 bits, but it is what it is.  I gather that the 4:1 clock ratio is set by the FPGA part itself and the SDRAM clock rate used.  I'll dive deeper into UG586.  

 

Now I just beed to know how the native interface works!

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Anonymous
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Re: New User DDR3 AXI4 Interface Question

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Im looking at UG586 March 1, 2011, page 95. Figures 1-52 through 1-54 and surrounding text look related. It doesn't introduce the protocol much. Is this what you are looking for?

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Re: New User DDR3 AXI4 Interface Question

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Yes, that's what I'm looking for.  Thanks pete_128.  I didn't look far enough into UG586 (and didn't expect the user interface to be defined there so didn't look hard enough).  I found a Nov 2015 version of UG586 when I hit the User Manual button in MIG. FYI. I wish the user data width could be specified like Altera allows.  Thanks all.

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Re: New User DDR3 AXI4 Interface Question

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One more question as I dig into the user interface spec. It looks like burst reads/writes are not supported. Given the controller has FIFOs, I assume you can queue them up, but queuing single transfers is not the same as burst transfers to/from the SDRAM. Does the controller look at the addresses and convert the r/w requests to SDRAM burst operations? If not, the performance will suffer greatly (50% on writes and 75% on reads from my Altera experience). Does this mean that I must use the AXI4 interface to use burst transactions with SDRAM and get the associated performance improvement?
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Re: New User DDR3 AXI4 Interface Question

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After some reflection, when the user interface reads/writes 128 bits at a time, that becomes a burst transaction with the SDRAM.  I assume when you read less than a burst you just ignore the extra data, and use the write mask for sub-burst writes.  Maybe that's why the user interface is always so wide (as well as keeping the clock rate slow).  Any thoughts?

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