NgdBuild:455 - Multiple drivers error related with DDR2 clocking

[mahircg5]

Greetings

I'd like to use external DDR2 memory for my project. Due to licensing limitations, EDK or XPS are not solutions.

So, I decided to use ISE and delve into ASMD design, by designing my own state-machine for control and external memory as datapath. For controlling the external memory (P3R1GE3JGF, 1 Gbit DDR2) on Atlys Spartan-6 Development board, I used CoreGen to generate the memory controller block, and made pin assignment. Since different cores on my design works at different clock frequencies ( 12 MHz, 20 MHz, 96 MHz and 320 MHz for memory), a DCM module has also been generated with CoreGen. 

After examining the documentation of MIG (named ug388) I saw that there is already an IOB connected to the system clock of MCB, so I selected "No Buffer" as the output of DCM OUT4 pin. Even though my technology schematic shows that the design is synthesized as it should be ( no cascaded IOB's on system clock of MCB), I get the following error when implementing the design;

ERROR:NgdBuild:455 - logical net 'sig_clk_mcb' has multiple driver(s):
pin PAD on block sig_clk_mcb with type PAD,
pin CLKOUT3 on block clk_instance_0/pll_base_inst/PLL_ADV with type PLL_ADV

I tried to remove the IOB for MCB system clock on MIG generated file; error dissappeared but placement failed this time, due to the IOB constratint on MCB core.

Top-level file and .UCF file can be found in the attachement.

Platform specific info: ISE v14.7, Windows 7 64-Bit 

Development board: Atlys Spartan-6 XC6SLX45 

Note: I've looked for possible duplicate posts in forum, couldn't find any way to find a workaround.

Much appreciated

[vsrunga]

Hi,

Moving your post to MIG board

Please go through relavant discussion and check if it helps

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Spartan-6-PLL-gt-MCB-Buffer-in-Series-problem/td-p/481160

Regards,

Vanitha

[vuppala]

Hi,

Can you share the placement error that you received after removing IOB for MCB system clock?

Thanks,

Vinay

[mahircg5]

Hi,

After commenting out the following lines in "memc3_infrastructure.vhd" ;

-- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
-- u_ibufg_sys_clk : IBUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
-- end generate;

.

. 

.

port map
(
CLKFBIN => clkfbout_clkfbin,
CLKINSEL => '1',
CLKIN1 => sys_clk,    -- Instead of sys_clk_ibufg, sys_clk is used as system clock
CLKIN2 => '0',
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DWE => '0',
REL => '0',
RST => sys_rst,
CLKFBDCM => open,
CLKFBOUT => clkfbout_clkfbin,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
CLKOUT0 => clk_2x_0,
CLKOUT1 => clk_2x_180,
CLKOUT2 => clk0_bufg_in,
CLKOUT3 => mcb_drp_clk_bufg_in,
CLKOUT4 => open,
CLKOUT5 => open,
DO => open,
DRDY => open,
LOCKED => locked
);

following error is prompted during implementation;

ERROR:PhysDesignRules:1452 - Unsupported PLL_ADV configuration. The signal
sig_clk_mcb on the CLKIN1 pin of PLL_ADV comp
mcb_instance/memc3_infrastructure_inst/u_pll_adv is not driven by an IOB,
BUFIO2, BUFIO2_2CLK, BUFG, BUFGCTRL, or DCM and routing for this connectivity
is not available.
ERROR:Pack:1642 - Errors in physical DRC.

[mahircg5 · Accepted solution]

Found the solution;turns out lack of knowledge about buffer types caused me a considerable amount of time on this issue.

"An IBUFG drives a global clock net from an external pin.

A BUFG drives a global clock net from an internal signal." 

Above information is found on "Difference between IBUFG and BUFG clock" topic in Xilinx forums, and changing the buffer type in memc3_infrastracture.vhd into BUFG solved the problem.

-- se_input_clk : if(C_INPUT_CLK_TYPE = "SINGLE_ENDED") generate 
--***********************************************************************
-- SINGLE_ENDED input clock input buffers
--***********************************************************************
-- u_ibufg_sys_clk : BUFG
-- port map (
-- I => sys_clk,
-- O => sys_clk_ibufg
-- );
-- end generate;

[mahircg5]

After modifying the design as mentioned, I've designed a simple test logic( read&write one byte of data) for MCB and it worked successively.

However, after examining the datasheet of MCB, I spotted that DCM's are not a part of clocking network and could not be used with MCB (in UG388 documentation).

"DCMs do not have access to the I/O clock networkand cannot, therefore, be used to drive MCBs."

My question is, do I need to apply external clock to the MCB before proceeding with the current design(applying clock from DCM to MCB). Would there be any damages or inaccuracies by not using an external clock in the design further on? Any suggesstions in that manner is much appreciated.