03-12-2020 06:39 AM
I have problems about creating custom DDR4 IPCORE in vivado 2019.2. Actually I want to redesign DDR4 IP core in PL part according to my needs but I could not change. Also I want to write and read huge data sets DDR4 and I could not find any resource about creating custom DDR4 IPCORE.
Can you provide any reference design about DDR4 Ip core as pure vhdl?
03-16-2020 05:00 PM
What is the issue you are facing?
Here is a general guide on how to create custom CSV for your custom part - https://www.xilinx.com/support/answers/63462.html
Also, here is a guide that includes how you can generate an example design to look at IP design files for your reference - Creating a Memory Interface Design using Vivado MIG
03-16-2020 07:29 PM
Writing your own DDR4 controller would likely be extremely challenging for many reasons:
-UltraScale was the first Xilinx FPGA family that electrically supported DDR4
-if by "pure VHDL" you mean behavioral RTL vs structured instantiation of device primitives, I suspect you'll find it very difficult to design the PHY alone... There are modes of operation of some of the I/O primitives that are needed here and probably not documented publicly to the extent needed to achieve this
-then there's the performance required here - another set of challenges with respect to implementation
-I'd try to use the existing IP that is already provided by Vivado to interface to DDR4: https://www.xilinx.com/support/documentation/ip_documentation/mig/v7_1/pg150-ultrascale-mis.pdf
At the very least, a study of the product guide will hint at some of the considerations
03-18-2020 01:00 AM
03-18-2020 04:58 AM
I still don't understand your "custom DDR4" reference... If you are adding a new/custom part to MIG, the answer record above would be useful... That is very different from writing your own IP core or DDR4 PHY... As I said before, the latter would be extremely challenging.
Normally (say a state machine or data plane inside the FPGA) - you'd start with the MIG DDR4 generated example design - that is in the product guide I referenced above.
Now it appears that you want to interface the PL-side DDR4 back to the MPSoC processor - that is possible as well. Both the ZCU102 and ZCU106 development boards have both the PS-side DDR controller ("hard"/dedicated ASIC gates) and a PL-side MIG interface ("soft"/implemented in the programmable logic and the FPGA I/O blocks). I'd start by reviewing the applicable tutorials on the MIG integration for those boards, e.g.
that should be helpful in terms of the design flow here.
03-18-2020 05:36 AM