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rutabagazuma
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Contributor
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Registered: ‎04-02-2019

PL DDR ACCESS

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I have a SoC design with a DMA controller in the PL interfaced to the S_AXI_HP0_FPD port of the Zynq.

In my design, I can, via the R5, read and write the DDR memory on the PCB attached to the Zynq.   

However, when I issue a DMA transfer to DDR memory, I see the burst (via ILA) get generated on the AXI master port of the DMA controller.   Subsequent reads of the same DDR location in memory show that the memory was not updated by the DMA write.   I can still read and write the DDR with the R5.

In my address editor for the design, I see that the DMA master maps to the lower order 2G of addressable memory.   The addresses generated by the DMA fall well within the 0x0000_0000 and 0x7FFF_FFFF address range.

Is there a setting in the Zynq which would filter out writes to DDR memory from the PL?

I am stumped.

 
 

 

 

 

 

 

 

 

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dgisselq
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Registered: ‎05-21-2015

@rutabagazuma,

This sounds like a cache problem.  If the memory you are writing to exists within the cache of the Zynq, you may need to do some more work to make certain that the Zynq knows that the memory has been changed and its cache has been poisoned.

Dan

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dgisselq
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Registered: ‎05-21-2015

@rutabagazuma,

This sounds like a cache problem.  If the memory you are writing to exists within the cache of the Zynq, you may need to do some more work to make certain that the Zynq knows that the memory has been changed and its cache has been poisoned.

Dan

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rutabagazuma
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Registered: ‎04-02-2019

Is there something about the way the Zynq is configured such that the DDR memory is incoherent at the address I am using?  how/why would writes from the PL invalidate the zynq cache.   can the cache be disabled for the purposes of fault isolation?

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