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Karthi_P
Observer
Observer
320 Views
Registered: ‎02-03-2021

PL DDR4 in ZC102 Write and read operation using MIG IP core

Hi,

    I am using ZC102 board. In my design, I am trying to access the PL DDR4 Memory using MIG IP core. I have created a logic for Write and read operation for MIG User interface signal. I am writing continuous six write operation and again i am reading the same address. I am getting data but read data is not in the sequence as per input address. I have attached the chipscope image for write address and data, read address and read response.  Please anyone can help me where is the mistake, I am not able to find out.

Write Address sequence in hexa : 08, 10, 18, 20, 28, 30

Write data sequence in hexa : 01,  02, 03, 04,  05, 05

Read Address sequence in hexa : 08, 10, 18, 20, 28, 30

Read data sequence in hexa : 02,  03, 04, 05,  05, 01

But expected read data sequence in Hexa : 01,  02, 03, 04,  05, 05

 

Thanks in advance,

Karthi P

wr_data.PNG
rd_cmd.PNG
rd_response.PNG
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2 Replies
kshimizu
Xilinx Employee
Xilinx Employee
245 Views
Registered: ‎03-04-2018

Hello @Karthi_P ,

 

I refer to the write sequence in UG150.  Could you please try to “app_wdf_data”, “app_wdf_wren” and “app_wdf_end” at the same time, and also input 8_data like Figure 4-4?

 

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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fig 4-4.PNG
sim.PNG
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Karthi_P
Observer
Observer
207 Views
Registered: ‎02-03-2021

Hi kshimizu, 

Happy to see your reply, I have implemented wr_en and wdf_end as per figure 4.4. But I have faced the same problem. Here i have incremented number of write and read data is 64. for every 442ms i am enabling write and read operation . When i am loading bit file in zc102 board, i can able to see correct data in ila. After few seconds, again i am seeing read data. At the time, first data 1 is missed, i am getting 2 as a first data of read data. after few seconds 3 as a first data of read data and continue like this. after few seconds in between data also missing. I have attached a .zip file for your reference, i am not able to find where is the mistake. please anyone tell, what is the exact problem? 

Thanks in advance,

Karthi P

 

Note: 

data_file.zip is correct one (radix - unsigned)

data_file1.zip - 1 is missing at sequence of read data (radix - unsigned)

illa clock is 333Mhz(3ns).

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