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Adventurer
Adventurer
214 Views
Registered: ‎01-20-2017

PRBS Read Leveling Error debug

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I'm following the debug guide for checking a new MIG memory controller (Kintex 7 xc7k160tffg676-2).  In UG586, there is Table 1-73 that talks about the Basic ILA Debug Signals.  When I run my hardware and look at these signals in ILA, no errors are reported.

However, if I scan down the list of signals shown in the ILA interface, I see that it is reporting a PRBS Read Leveling Error, since the signal dbg_prbs_rdlvl_compare_err goes high.   Attached is a screen grab showing the status of the PRBS signals as this error signal goes high.  I'm following the debug guide in UG586 (June 8, 2016) on pages 228-273.  Specifically, I'm looking at the section on 'Debugging PRBS Read Leveling Failures'.  In contrast to the other sections on calibration failures, there are no real Debug steps suggested.  Are there some suggested signals that I should check to address this error?  Are there timing constraints I can add to the FPGA build that will help fix this error?

 

prbs_calibration_failure_signals_all.PNG
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Xilinx Employee
Xilinx Employee
116 Views
Registered: ‎03-04-2018

Re: PRBS Read Leveling Error debug

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Hello @efpkopin ,

 

Thanks for your reply.

“init_calib_complet is high” and “tg_compare_error is low” indicate that the MIG IP calibration is successful, so if these signals are like that, your MIG IP works fine.

 

I checked the “prbs_rdlvl_compare_error”.  “The signal gets high” is as expected.  PRBS read leveling algorithm finds the mismatch by increasing the tap, so “prbs_rdlvl_compare_error” will be high in this case.

 

 

Overall, if “init_calib_complet is high” and “tg_compare_error is low”, no issue occur in your design.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

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4 Replies
Xilinx Employee
Xilinx Employee
180 Views
Registered: ‎03-04-2018

Re: PRBS Read Leveling Error debug

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Hello @efpkopin ,

 

Let me clarify your question.  From your sentence below, does the calibration pass on your board?  Do you want to know how it works at PRBS levering via ILA?

>When I run my hardware and look at these signals in ILA, no errors are reported.

 

If the calibration passes and you want to know the PRBS, you can use the traffic generator, which you can control via VIO.  Please see the UG586, p.67.

 

 

Best regards,

Kshimizu

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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Adventurer
Adventurer
151 Views
Registered: ‎01-20-2017

Re: PRBS Read Leveling Error debug

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@kshimizu, thank you for your response.  So, most of the time, all of the error signals in that 'Basic ILA Debug Signal' table (Table 1-73) are low (this includes the tg_compare_error) *and* init_calib_complete goes high.  But the prbs_rdlvl_compare_err goes high.  So I guess my question is this:

 

- If init_calib_complete is high and tg_compare_error is low, does that mean that my memory controller is operating correctly on the PCB *even if* the prbs_rdlvl_compare_error (and related) signals are high?

 

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Scholar watari
Scholar
127 Views
Registered: ‎06-16-2013

Re: PRBS Read Leveling Error debug

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Hi @efpkopin 

 

Did you measure eye-pattern with PRBS by oscilloscope and/or make sure eye-pattern with PRBS by SI tool ?

Also, how do you define ODT value ?

 

It seems eye-pattern issue.

 

Best regards,

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Xilinx Employee
Xilinx Employee
117 Views
Registered: ‎03-04-2018

Re: PRBS Read Leveling Error debug

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Hello @efpkopin ,

 

Thanks for your reply.

“init_calib_complet is high” and “tg_compare_error is low” indicate that the MIG IP calibration is successful, so if these signals are like that, your MIG IP works fine.

 

I checked the “prbs_rdlvl_compare_error”.  “The signal gets high” is as expected.  PRBS read leveling algorithm finds the mismatch by increasing the tap, so “prbs_rdlvl_compare_error” will be high in this case.

 

 

Overall, if “init_calib_complet is high” and “tg_compare_error is low”, no issue occur in your design.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

-------------------------------------------------------