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patmcn
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Registered: ‎06-27-2019

PS DDR register errors next step?

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Hi, I'm trying to debug my DDR4 on a custom board.  The common error I found on the forums that was similar to mine was the psu_init.tcl script hanging with no UART output.  I was able to get the PMU and FSBL loaded successfully and have been probing the DDR PHY status registers but I need help knowing what the next step should be.

My DDR PHY (0xfd080030) returns (80C000FF <Hex Integer>).

I'm not sure what the difference between hex integer and hex is supposed to mean but I assumed it is supposed to be 0x80C000FF which would mean that my DDR is getting a DQS Gate Training Error and a Write Leveling Error.

Using SDK 2018.3, zcu2eg, custom board with ddr4 (MT40A512M16LY-062E IT:E) and I attached my ddr settings from vivado.

Any suggestions? Thanks!

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watari
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Registered: ‎06-16-2013

Hi @patmcn 

 

As you know, DRAM controller for DDR3/DDR4 has write leveling and read leveling function to adjust flight time (time distance).

"Write leveling" adjusts skew (phase) between CK and DQS.

However, dram controller has a capability (limitation) of this skew. It depends on length between CK and DQS, clock frequency and capability of controller.

 

So, I mentioned before as question.

 

Hope it helps.

 

Best regards,

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watari
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Hi @patmcn 

 

Did you make sure your DDR4 pattern on PCB ? Especially, relationship between CK and DQS ?

Also, did you read PCB guideline for DDR4, too ?

 

If no, would you try them first ?

 

Best regards,

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patmcn
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I will double check those but yeah, I made sure to follow the ddr routing guidelines.

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patmcn
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patmcn
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This was also helpful to find to slow down the ddr.  Posting link for future refernce.  Checking if it might help my design now.

 

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Zynq-Ultrascale-PS-DDR-EDAC-errors-when-accessing-memory/td-p/856878

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patmcn
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This link was very useful in breaking down all of the DDR parameters I wish was clearer with Xilinx documentation:

 

https://www.element14.com/community/groups/fpga-group/blog/2018/07/31/lpddr4-timing-parameters-for-zynq-ultrascale-mpsoc-in-vivado

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patmcn
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patmcn
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I've been able to get my 0xFD080030 register to read out 0x80000FFF.  That would indicate that the DDR4 has initialized correctly, right?

I was able to adjust multiple ddr settings between using the ddr-1600 and ddr-2400 by taking the default clock (800MHz and 1200MHz, respectively) and reducing the clock speed 200 MHz for each.  Now I can at least see that the FSBL is not hanging and I'm getting info out of the UART. 

Since I was able to see it configure by reducing both configurations clock speed, that would seem to indicate to me that I have a CK length issue.  Anyone have any thoughts? @watari maybe this is what you were getting at?

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watari
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Registered: ‎06-16-2013

Hi @patmcn 

 

As you know, DRAM controller for DDR3/DDR4 has write leveling and read leveling function to adjust flight time (time distance).

"Write leveling" adjusts skew (phase) between CK and DQS.

However, dram controller has a capability (limitation) of this skew. It depends on length between CK and DQS, clock frequency and capability of controller.

 

So, I mentioned before as question.

 

Hope it helps.

 

Best regards,

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