PS DDR timing with Petalinux

[kinkeads]

We are testing a custom board based on a ZCU102.  The PS DDR 2133 memory is the same as on the ZCU102, but we believe the PCB layout is not able to support the nominal 1067 MHz clock rate, so we have reduced the DDR clock to 800MHz using the Vivado IP Integrator PS DDR configuration GUI.

Bare metal PS DDR memory tests now pass with the 800MHz clock.  However, the Petalinux FSBL hangs when it tries to initialize the PS DDR.

Does the Petalinux FSBL use the DDR timing I specified in Vivado IP Integrator?   Or, does Petalinux ignore those setting and instead read the DDR Serial Presence Detect (SPD) EEPROM to determine the speed grade of the DDR memory? 

Thanks.

[stephenm]

Petalinux should use the same FSBL as created in SDK/Vitis. The PS configurations are passed using the psu_init.c/h files in the XSA file that you exported from Vivado

[atran17]

yes, Petalinux use the same as FSBL created in SDK.

FSBL in SDK is also failed. Here is the log failed in FSBL using SDK

XFSBL_DDR_INIT_FAILED

================= In Stage Err ============

Fsbl Error Status: 0x3FFFFFFF
Fallback not supported

Exit from FSBL

[stephenm]

Have you tried a DDR memory test in DDR?

[atran17]

Yes, I did test DDR using SDK too and it work fine. However, the FSBL always failed. 

I attached the DDR test here.

[kinkeads]

We determined the FSBL is failing when it tries to read the DDR4 SPD EEPROM using the PS I2C1 controller. 

XFsbl_DdrInit()--> call  XFsbl_IicReadSpdEeprom()

fsblmp/src/xfsbl_ddr_init.c:188:#define XFSBL_SODIMM_SLAVE_ADDR 0x51U

The process of reading the SPD is called "Dynamic DDR Configuration" as explained in AR# 75769.  Our custom board does not have an I2C mux at address 0x75, which the AR states is a requirement to support Dynamic DDR Configuration.  This apparently is a known issue:  https://github.com/Xilinx/embeddedsw/issues/95

How do we prevent the FSBL from reading the DDR SPD?  We already specified the DDR timing within Vivado IP Integrator and do not wish to use the Dynamic DDR Configuration feature.  We are using Vivado version 2019.1

[mnarani · Accepted solution]

Hi,

You can disable the Dynamic DDR configuration in Vivado tcl console by setting the Dynamic DDR Config parameter to '0' as below:

set_property CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN 0 [get_bd_cells /zynq_ultra_ps_e_0]

Thanks.

[atran17]

I don't have to disable Dynamic DDR configuration in Vivado. I just slow down the DDR clock to 600 MHz and I can see FSBL boot up and load U-Boot,...etc.

In bare-metal simple DDR test, I can see 800 MHz seem to able to passed read/write eyes test, but failed in FSBL when do DDR initialize and it hang in  DDR training sequence.

However, just change DDR clock set to 600 MHz in Vivado, than everything work fine, but DDR4 works at 600 MHz is not good.

[mnarani]

When the CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN is disabled in Vivado, FSBL will not go to read the SPD of the DDR. The DDR initialization and training will be done by on psu_init only. 

That way you can run FSBL successfully with 800MHz also.

[atran17]

Do you know how we can read the DDR speed that set in Vivado in the PS Bare-metals code?

I would like to read the configure of DDR and know the speed that set in Vivado code?