Post Synthesis Simulation of UltraScale DDR4 memory controller
I am trying to do post synthesis simulation on a design with DDR4 interface. I ran it for hours and still I can not see init_calib_complete pin high. I went through the documentation of "UltraScale Architecture-Based FPGAs Memory IP v1.4". In the documentation I found a note saying " Behavioral simulations are supported with Mixed Simulator Language. Netlist (post-synthesis and post-implementation) simulations are supported with Verilog Simulator Language and are not supported by Vivado Simulator". I am currently using Vivado 2019.2 and its integrated Vivado simulator. If I can not use it for such post synthesis simulation, can you tell me the other options I have and where can I find how to do such a simulation?