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bjackson_ost
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Registered: ‎03-12-2018

Preloading generated DDR3 Model

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I'm using Vivado 2017.3.1 and I'm using a Virtex 7 part (xc7v2000tflg1925-1) and used MIG to generate DDR3 controller (ug586). The tool generated "ddr3_model.sv" and "ddr3_model_parameters.vh" files to describe a Micron SDRAM DDR3 memory part. Initially, I'm simulating those 2 files as standalone using Modelsim. I need to initialize the memory and I see which parts of "ddr3_model.sv" that I should focus on. First, my first 2 lines of "ddr3_model.sv" are 'define MAX_MEM and 'define mem_init. With these 2 lines, I could enable the preload section (line 427). With my testbench simulation, I load my mem_init.txt (line 428) and I see that the contents are written to (line 437) and read from (line 440) for confirmation. Further in my simulation (after the initialization sequence is complete), I strobe CASN low to read out contents. The output is not quite what I expect. When I strobe CASN, 8 columns (8 bits per column) of preload data is expected. The model does output said 8 columns of data, but the values are not what I expect.

 

Below is a snapshot of the Modelsim log that shows my situation. Starting with line 32, you see where data is preloaded and confirmed via READ statements. Lines 8795 through 8805 show the results of the CASN active-low strobe. I expected the <data> output to be 0x80, 0x80, 0x80, 0x42, 0x42, 0x42, 0x29, and 0x42 (based written data on lines 32 through 47). Instead, it's 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, and 0x00. Could anyone offer guidance?Clipboard02.jpg

 

 

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coryb
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Registered: ‎02-11-2014

Hello @bjackson_ost,

 

In XAAP1180, please follow the steps in "Executing the Simulation" so you can understand exactly the flow that is used to initialize the memory model. Keep in mind that this XAPP was written for Vivado 2015.2.

 

Step 5. Right-click design_1_i and click on Generate Output Products.

 

This is the step I am mentioning specifically to provide you with the RTL by generating the Block Diagram. Otherwise you will be missing files for simulation.

 

Thanks,

Cory

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coryb
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Registered: ‎02-11-2014

Hello @bjackson_ost,

 

An easier way to initialize the memory can be found in XAPP1180. If you analyze the Test Bench provided in provide ZIP, you will see that we utilize some readmemh commands. Here is an example of that:

 

$readmemh("ddr3_0.mem",system_tb.ddr3_3.memory);

 

Please let me know if this gives you better simulation results.

 

Thanks,

Cory

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bjackson_ost
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Registered: ‎03-12-2018

Hey, Cory.

 

This has been very helpful. I downloaded the zip file and opened it with no issue. But, it turns out that it appears the Verilog design file "design_1" is missing. I'm trying to simulate the TB in the ~/xapp1180/mb_ddr_simulation/sim/512Mb_ddr3/ path that requires that. Do you know where I could get this or is there an updated link of this zip file?

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coryb
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Hello @bjackson_ost,

 

The block diagram design_1 is located in /xapp1180/mb_ddr_simulation/project_1.srcs/sources_1/bd/design_1.

 

Thanks,

Cory

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bjackson_ost
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Hey, Cory.

 

I'm trying compile and simulate the "design_1" component found in design_1_wrapper.v. The block diagram doesn't help. Did I miss something?

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bjackson_ost
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Registered: ‎03-12-2018

Cory,

 

Below is a snapshot of the compile error I'm referring to for your reference.

 

Clipboard10.jpg

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coryb
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Hello @bjackson_ost,

 

I would make sure you have generated the block diagram before simulating. I do not think the XAPP comes with all the RTL generated for the block diagram.

 

Thanks,

Cory

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bjackson_ost
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Hey, Cory.

 

Thanks for the prompt response. I'm not familiar on how to generate the block diagram. If I generate, would the supporting RTL be produced? What's the block diagram generation process?

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coryb
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Registered: ‎02-11-2014

Hello @bjackson_ost,

 

In XAAP1180, please follow the steps in "Executing the Simulation" so you can understand exactly the flow that is used to initialize the memory model. Keep in mind that this XAPP was written for Vivado 2015.2.

 

Step 5. Right-click design_1_i and click on Generate Output Products.

 

This is the step I am mentioning specifically to provide you with the RTL by generating the Block Diagram. Otherwise you will be missing files for simulation.

 

Thanks,

Cory

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