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Adventurer
Adventurer
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Registered: ‎06-18-2016

Problem building with MIG-generated DDR3 IP and XDC files

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Hi All,

I'm trying to build a simple example using MIG 7 to control the PL DDR3 memory on a ZC706. There are warnings during synthesis that all ddr3_dm and ddr3_dqs signals are ignored and consequently in the synthesis output the ddr3_dm and ddr3_dqs signals are not connected between the block design and the board. These signals come out of the MIG-generated block design file and I just wire them through to the top level of my design, and that's all my design does. The MIG IP wants them connected, so I don't know why they disappear during synthesis. The ddr3_dq signals don't generate any warnings and they're all connected in the schematic. I've checked for any potential upper/lower case mismatches between IP and xdc files.

The MIG-generated xdc file sets properties for all ddr3_dm and ddr3_dqs signals and critical warnings are generated for all of those signals during implementation, followed by placer errors. Output from place_ports is included below. I'm using Vivado design edition 2019.1 on Windows 7. Can you please tell me how to resolve this?

Here are the relevant messages during synthesis:

INFO: [Synth 8-638] synthesizing module 'demo_top' [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:81]
WARNING: [Synth 8-506] null port 'ddr3_dm' ignored [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:43]
WARNING: [Synth 8-506] null port 'ddr3_dqs_n' ignored [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:45]
WARNING: [Synth 8-506] null port 'ddr3_dqs_p' ignored [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:46]
WARNING: [Synth 8-506] null port 'DDR3_0_dm' ignored [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:91]
WARNING: [Synth 8-506] null port 'DDR3_0_dqs_n' ignored [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:93]
WARNING: [Synth 8-506] null port 'DDR3_0_dqs_p' ignored [D:/Clients/NPS/rtp_box/ddr3_demo_c/ddr3_demo_c.srcs/sources_1/new/demo_top.vhd:94]

Thanks, Tom

place_ports

Starting IO/Clock Placer Task

Phase 1 Add Constraints new method

Phase 1.1 Build CellView Core

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 3361.480 ; gain = 0.000

Phase 1.2 Add User PBlocks

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 3361.480 ; gain = 0.000

Phase 1.3 Apply User PBlocks

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 3361.480 ; gain = 0.000

Phase 1.4 Add terminal Constraints

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 3361.480 ; gain = 0.000

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.032 . Memory (MB): peak = 3361.480 ; gain = 0.000
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is unplaced after IO placer
ERROR: [Place 30-69] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is unplaced after IO placer

Phase 2 IO and Clk Clean Up

Phase 2.1 FixIDCReqs

Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 3361.480 ; gain = 0.000
ERROR: [Place 30-162] Unroutable Placement! A PLL / BUFHCE component pair is not placed in a routable site pair. The PLL component can use the dedicated path between the PLL and the BUFHCE if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/pll_clk3_out] >

BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKOUT3) is provisionally placed by clockplacer on PLLE2_ADV_X1Y5
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X0Y0

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gclkio_bufg
Status: PASS
Rule Description: An IOB driving a BUFG must use a CCIO in the same half side (top/bottom) of chip
as the BUFG
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y274
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_200.u_bufg_clk_ref (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y18

Clock Rule: rule_gclkio_mmcm_1load
Status: PASS
Rule Description: An IOB driving a single MMCM must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
is NOT set
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y274
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y5

Clock Rule: rule_gclkio_pll_1load
Status: PASS
Rule Description: An IOB driving a single PLL must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
is NOT set
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk (IBUFDS.O) is locked to IOB_X1Y274
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/plle2_i (PLLE2_ADV.CLKIN1) is provisionally placed by clockplacer on PLLE2_ADV_X1Y5

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKOUT1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y5
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_300_400_en.clk_ref_400.u_bufg_clk_ref_400 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y17

Clock Rule: rule_mmcm_mmcm
Status: PASS
Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
each other (vertically), if the CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y5
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_iodelay_ctrl/clk_ref_mmcm_gen.mmcm_i (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y5

Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
than the capacity of the region
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X0Y0

Clock Rule: rule_bufhce_mmcm
Status: PASS
Rule Description: A BUFH driving an MMCM must both be in the same clock region
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X0Y0
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y0
BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_ddr3_infrastructure/u_bufg_clkdiv0 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iddr_edge_det/u_phase_detector (IDDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs/IBUFDS (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs/IBUFDS_0 (IBUFDS_IBUFDISABLE_INT) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/gen_dqs_iobuf_HP.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs/OBUFTDS (OBUFTDS_DCIEN) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i (PHASER_REF) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i (PHY_CONTROL) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i (PHASER_REF) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i (PHY_CONTROL) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqs (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/dqs_gen.oddr_dqsts (ODDR) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo (IN_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo (OUT_FIFO) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in (PHASER_IN_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out (PHASER_OUT_PHY) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phaser_ref_i (PHASER_REF) is not placed
ERROR: [Place 30-68] Instance BLOCK_DESIGN/mig_7series_0/u_design_1_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/phy_control_i (PHY_CONTROL) is not placed

Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3361.480 ; gain = 0.000

Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 3361.480 ; gain = 0.000
place_ports: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3361.480 ; gain = 0.000
ERROR: [Common 17-39] 'place_ports' failed due to earlier errors.

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Adventurer
Adventurer
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Registered: ‎06-18-2016

Re: Problem building with MIG-generated DDR3 IP and XDC files

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Hi All,

There were a couple of syntax errors in the PS7 declarations and fixing that completely solved the problem.

Cheers,

Tom

 

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Highlighted
Adventurer
Adventurer
234 Views
Registered: ‎06-18-2016

Re: Problem building with MIG-generated DDR3 IP and XDC files

Jump to solution

Hi All,

There were a couple of syntax errors in the PS7 declarations and fixing that completely solved the problem.

Cheers,

Tom

 

View solution in original post

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