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Participant raphael1989
Registered: ‎10-21-2011

Problem in using MIG

Hello! I noticed that, MIG can automatically generate DQS/DQS# and ck/ck# pins by consider the data width and memory part I choosed in dialog(I guess). But in fact, the very memory device I use is a package of 2 pieces of the memory part, which means that there are less DQS/DQS# and ck/ck# pins(1/2 in fact). So, can I modify the design and .ucf files generated by MIG to fit my design? Which part and what efforts need to be done? Thank you!

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2 Replies
Registered: ‎08-14-2007

Re: Problem in using MIG

It's not clear what you mean by "a package of 2 pieces of the memory part."


Normally unless this is a buffered DIMM or similar package, each DQS would

be wired separately.


Can you post a link to the data sheet for your part?


MIG allows you to define a new memory part starting from one of the existing

parts that has similar timing.  Then you can modify parameters like number

of DQ pins per DQS pin, etc.  This is better than running MIG with a different part

and then changing the DQS_WIDTH setting afterwards, because it ensures

that you will have the proper constraints in the UCF file generated by MIG.


-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
Registered: ‎10-23-2007

Re: Problem in using MIG

Go back and rerun MIG with the part that you are using and select the width of the overall interface.  That will cause MIG to generate the correct paramters for your particular design.


For example, if you are using 2 x8 devices for a 16 bit wide interface, you should select the correct x8 part and set the width in MIG to 16 bits.


It is not a good idea to attempt to modify the output of MIG directly, but it can be done.


If you have further questions, please note the FPGA family you are using and the interface type (DDR2?  DDR3?).


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