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Observer bujosa
Observer
3,968 Views
Registered: ‎05-24-2011

Problem with DDR3 constraints (ucf) from MIG

Using multi controller DDR3 MIG on Virtex-6 xc6vlx365tff1156-2

 

The following contraints cause erros in ISE while translating the *.edf file generated by synplicity_pro:

 

 

Problem #1:

1. ##Site: G18 -- Bank 36
INST "u_cash_core/u_ddr3_top/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y183";

 

There is a total of 8 similiar contraints that all fail with the following:

 

ConstraintSystem:58 - Constraint <INST "u_cash_core/u_ddr3_top/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_oserdes_cpt" #INST "u_cash_core/u_ddr3_top/c1_u_memc_ui_top/u_mem_intfc/phy_top...> [cash_top.ucf(368)]: INST "u_cash_core/u_ddr3_top/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_ck_cpt[0].u_oserdes_cpt" does not match any design objects.

 

 

I fix a similiar error with the following but it did not work in this case:

 

Converted This:

##Site: A16 -- Bank 36
#INST "u_cash_core/u_ddr3_top/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/genblk*.gen_loop_col0.u_oserdes_rsync"

To This:

INST "u_cash_core/u_ddr3_top/c1_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
  LOC = "OLOGIC_X2Y177";

 

 

Problem #2:

 

These cause errors:

PIN "u_cash_core/u_pcie_core/trn_reset_n_int_i.CLR" TIG ;
PIN "u_cash_core/u_pcie_core/trn_reset_n_i.CLR" TIG ;
PIN "u_cash_core/u_pcie_core/pcie_clocking_i/mmcm_adv_i.RST" TIG ;

 

ConstraintSystem:59 - Constraint <PIN "u_cash_core/u_pcie_core/trn_reset_n_int_i.CLR" TIG ;> [cash_top.ucf(913)]: PIN "u_cash_core/u_pcie_core/trn_reset_n_int_i.CLR" not found.  Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

 

 

Problem #3

In the readme.txt file under ../example_design/par/ directory there is the following message:

"icon5_cg.xco", "ila384_8_cg.xco", "vio_async_in256_cg.xco" and
  "vio_sync_out32_cg.xco" files are used to generate ChipScope icon,
  ila and vio EDIF/NGC files. When you want to view the design signals
  on ChipScope, you should port the design signals to ChipScope modules
  i.e. ila, vio and icon and set DEBUG_PORT parameter to "ON" in example_top
  rtl file. In order to generate the EDIF/NGC files, you must execute
  the following commands before starting synthesis and PAR.

        coregen -b icon5_cg.xco
        coregen -b ila384_8_cg.xco
        coregen -b vio_async_in256_cg.xco
        coregen -b vio_sync_out32_cg.xco

 

But when I run these I get the following error:

ERROR:sim:479 - Batch command 'generate
   ' is illegal without an open project.

 

I have an open project, how do I tell the batch command that a project is opened?  What is it looking for?

 

Problem #4:

When ISE can not find an INST name, is there some constraints editor I can use to traverse the hierarchy to make sure I am giving it the correct INST name.  I tried using the "constraints editor" in ISE but apparently I need to get past the Translate Process before using it.

 

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3 Replies
Observer bujosa
Observer
3,962 Views
Registered: ‎05-24-2011

Re: Problem with DDR3 constraints (ucf) from MIG

 

I figured out "Problem #3"

 

1. open the coregen gui.

2. open the project used to create the ddr3 core  (ddr3_if in my case)

3. This creates a file called ddr3_if.cgc (in my case) under ipcore_dir which the "coregen" command line is looking for

4. from the dir that you started ISE from enter:

coregen -b ipcore_dir/ddr3_if/example_design/par/icon5_cg.xco -p ipcore_dir/ddr3_if.cgc

 

This will create icon5.ngc file which needs to be added to your source files for your build project

Observer bujosa
Observer
3,953 Views
Registered: ‎05-24-2011

Re: Problem with DDR3 constraints (ucf) from MIG

 

One solution for "Problem #4" is to call up the *.srm file in synplicify_pro.  This is the technology view netlist.  Traversing the hiearchy shows that the path in "Problem #1" does not exist past the u_phy_rdclk_gen level.  Not sure why "u_oserdes_cpt" does not exist.

 

Doing the same for "Problem #2", I find "trn_reset_n_i" and "trn_reset_n_int_i" but it has "(ghost) next to it.  Not sure what that means, but I am guessing that it got pruned for some reason.   Anyone knows what "(ghost)" means?

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Observer bujosa
Observer
3,949 Views
Registered: ‎05-24-2011

Re: Problem with DDR3 constraints (ucf) from MIG

 

Update on Problem #1:

 

I see this in the synplify_pro mapper.srr log.:

@N: BN114 :"/vobs/j750/tomahawk/cash/rtl/ddr3/phy/phy_rdclk_gen.v":442:8:442:20|Removing instance u_cash_core.u_ddr3_top.c1_u_memc_ui_top.u_mem_intfc.phy_top0.u_phy_read.u_phy_rdclk_gen.gen_ck_cpt\[0\]\.u_oserdes_cpt of black_box view:VIRTEX.OSERDESE1(PRIM) because there are no references to its outputs

 

I pulled in all the files that were generated by the core.  So why would there be "no references to its outputs"?

 

What am I missing here?

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