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Visitor
Visitor
570 Views
Registered: ‎09-09-2019

Problem with simulation of DDR3 Model in vivado

I can run the Example design of MIG 7 series successful, and the TCL console output should be like this:

# source -notrace {../../../../imports/xsim_options.tcl}
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 CAS Write Latency = 8
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 CAS Write Latency = 8
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1220189.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1870189.0 ps INFO: Load Mode 3
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1870189.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
sim_tb_top.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 1870189.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1870189.0 ps INFO: Load Mode 3
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1870189.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
sim_tb_top.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 1870189.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
run: Time (s): cpu = 00:00:03 ; elapsed = 00:00:09 . Memory (MB): peak = 865.727 ; gain = 0.000
xsim: Time (s): cpu = 00:00:14 ; elapsed = 00:00:17 . Memory (MB): peak = 865.727 ; gain = 70.527
INFO: [USF-XSim-96] XSim completed. Design snapshot 'sim_tb_top_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:17 ; elapsed = 00:00:26 . Memory (MB): peak = 865.727 ; gain = 88.891

But when I use the ddr3_model.sv and ddr3_model_parameters.vh,  MIG IP core   and my own model to generate signals for user interface. When I run the simulation, the TCL console output is like this. Before the message of load mode appera, I think the outputs are same.

ddr3_tb.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 601017689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 601017689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 601667689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 601667689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 602317689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 602317689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 602967689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 602967689.0 ps INFO: Load Mode Z
ddr3_tb.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 603617689.0 ps INFO: ZQ        long = z
ddr3_tb.mem_rnk[0].mem.gen_mem[1].u_comp_ddr3.cmd_task: at time 603617689.0 ps INFO: ZQ        long = z
PHY_INIT: Memory Initialization completed at 604855100.0 ps
ddr3_tb.mem_rnk[0].mem.gen_mem[0].u_comp_ddr3.cmd_task: at time 604907689.0 ps ERROR: Activate  Failure.  Initialization sequence is not complete.

I really don't know why Load Mode is constant Z. I think I have connect the dd3_model and mig ip core. Can anyone told the reason?

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Moderator
Moderator
534 Views
Registered: ‎08-21-2007

It seems the DDR3 model is not properly initialized. Did you check the difference on the connection/parameters with DDR3 model?

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Visitor
Visitor
529 Views
Registered: ‎09-09-2019

I finally find the resolution. Adding the wire delay in the inout port will solve the problem. But I also find an example, which not using wire delay model. I compare the difference between the two examples and find the ddr3_model.sv and its parameter file is almosts same. The only difference is the define device type. I use two banks and the example without wire delay model uses one bank.

So I am still confused with the reason.  Any help will be appreciated.

The wire delay model is attached. I think it is only a three-state buffer.

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Observer
Observer
514 Views
Registered: ‎06-27-2019

Hi @gaoyuzhe ,

I guess I am having similar issue as you. Can you elaborate more in detail about how you resolved the issue? As part of my MIG, the dqs_n and dqs_p signals are 8-bit wide but for ddr3, they are declared 2-bit wide only. Why is it like that? How to resolve such issues?

Also, I have added the wiredelay file already but still I am getting the same error. Something like below:

Testbench.mem_rnk[0].gen_mem[6].ddr3_model.cmd_task: at time 6032210.0 ps INFO: Load Mode Z
Testbench.mem_rnk[0].gen_mem[7].ddr3_model.cmd_task: at time 6032210.0 ps INFO: Load Mode Z
Testbench.mem_rnk[0].gen_mem[0].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[1].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[2].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[3].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[4].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[5].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[6].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
Testbench.mem_rnk[0].gen_mem[7].ddr3_model.cmd_task: at time 7332210.0 ps INFO: ZQ long = z
PHY_INIT: Memory Initialization completed at 9805100.0 ps
Testbench.mem_rnk[0].gen_mem[0].ddr3_model.cmd_task: at time 9912210.0 ps ERROR: Activate Failure. Initialization sequence is not complete.

Can you please help on this? I have been stuck on this for quite some time now. Any help is much appreciated.

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Moderator
Moderator
484 Views
Registered: ‎08-21-2007

One more thing, did you check the simulation language option (tools-> settings) is set to mixed?

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Observer
Observer
460 Views
Registered: ‎06-27-2019

Yes @kren it is set to mixed language only. I believe that is not causing the trouble. Please help on this. This is really urgent.

 

Regards..

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Highlighted
Visitor
Visitor
437 Views
Registered: ‎09-09-2019

Do you use generate command to instantiate ddr3_model?
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Highlighted
Observer
Observer
425 Views
Registered: ‎06-27-2019

Hi @gaoyuzhe ,

Thanks for responding. Yes, I am using generate command to do so. Is there anything I should do differently?

Looking forward.

 

Regards..

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Highlighted
Visitor
Visitor
395 Views
Registered: ‎09-09-2019

As part of my MIG, the dqs_n and dqs_p signals are 8-bit wide but for ddr3, they are declared 2-bit wide only.

So you use more than one bank. You are supposed to instantiate four ddr3_models. You can read the eample project code and imitate how to instantiate ddr3_model in its top verilog file.

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