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Registered: ‎01-27-2020

Provide internal system clock and reference clock through MMCM/PLL for MIG

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I am using an Artix-7 (xc7a35ticsg324-1L) and the MIG IP from the IP catalog.

I understand that the sys_clk_i should be provided from an external source pin from the same bank and there is an option to generate clk_ref_i from MMCM/PLL from within the FPGA.

1. Is there any overide that I can use to generate clk from an MMCM/PLL. I have a Xtal clk coming in from a different bank that i would like to give sys_clk and clk_ref through an MMCM. (I am not worried about Jitter)

2. I used no_buffer while creating the sys_clk and ref_clk while customizing the MIG IP to provide an external clock (defined in the constraints). I get a route_design ERROR stating "The computed value xxxMHz for the VCO operating frequency of MMCME2_ADV falls outside the operating range of the MMCM VCO frequency (600 - 1200 MHz)" I believe there is a MMCM inside the MIG block, what could be causing this issue? How do i overcome this?

 

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Registered: ‎11-09-2017

Re: Provide internal system clock and reference clock through MMCM/PLL for MIG

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Hi ranjan.bangarilokappa@globalfoundries.com 

What is on board clock frequency? Check with attached clocking topology, same can apply to RTL flow.

Also add set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets <clock name>].

Regards
Pratap

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7series_clock.PNG
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Registered: ‎11-09-2017

Re: Provide internal system clock and reference clock through MMCM/PLL for MIG

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Hi ranjan.bangarilokappa@globalfoundries.com 

What is on board clock frequency? Check with attached clocking topology, same can apply to RTL flow.

Also add set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets <clock name>].

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

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Registered: ‎01-27-2020

Re: Provide internal system clock and reference clock through MMCM/PLL for MIG

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The on-board clock is coming from a different bank (bank 14) and my DDR3 connections are in bank 34.

On board clock frequency is 50MHz, using MMCM generating 83.33MHz (sys_clk_i) and 50MHz (ref_clk_i) exactly how you mentioned in the topology. Also used the override.

I get the route_design errors while implementing (DRC error) stating - 

1. MMCM_adv_ClkFrequency_div_no_dclk: The computed value 166.667 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y0 falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (24.000000), multiplication factor CLKFBOUT_MULT_F (4.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

2. PLL_adv_ClkFrequency_div_no_dclk: The computed value 333.333 MHz (CLKIN1_PERIOD, net clk_out1) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y0 falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (12.000000), multiplication factor CLKFBOUT_MULT_F (4) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. 

 

I used the clock wizard to create the MMCM clock, it uses multiplication factor of 23.125 for input clk, divide vale of 13.875 for sys_clk (83.33MHz) and divide value of 23.125 for ref_clk (50MHz)

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Registered: ‎11-09-2017

Re: Provide internal system clock and reference clock through MMCM/PLL for MIG

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Hi ranjan.bangarilokappa@globalfoundries.com 

Generate system clock 100MHz and reference 200MHz from clocking wizard and check the behaviour.

Make sure 100MHz is also configured in IP setting - input clock period (memory option tab in IP GUI).

Regards
Pratap

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