We have customized board with virtex5 and QDR-II sram
Virtex 5 Module is:5vfx200tff1738QDR-II SRAM is CY7C1612KV18
This part number is not supported in XILINX ISE 14.7 so we are customized this part from base part which is
CY7C1314BV18-167BZXC. It has Data width:36 and Address lines :18
CY7C1612KV18, it has Data width:18 and Address lines :22. 2 number of CY7C1612KV18 IC's are used in parallel to get 36 address lines. From base part we have modified Address lines from 18 to 22
while testing the QDR-II SRAM, writing AAAAAAAAA and toggling the same. Same data reading from IC.
But when I am testing, address is being lagged for every 5th clock cycle and data is also corrupted once and next data is correct. and also I am attaching the screen shot of this
Please suggest me where I am missing??