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spman2
Visitor
Visitor
8,611 Views
Registered: ‎01-01-2013

QDRII+ calibration problem

Hi,

 

Im trying to implement MIG QDRII+ core with virtex-7. I tried the example design, but the calibration signal doesnt go high.

I added the debug port (in MIG) to observe the debug signals in the running hardware. According to dbg_phy_status[7:0] which is 0E the problem must be in stage 1 calibration. But on the other hand rdlvl_stg1_done is asserted (high) and cal1_state_r is 0B (CAL1_DONE state). So state 1 must be completed and stage 2 must be started!

 

The waveform of debug signals is attached.

 

Could anyone please help me.

 

Thanks in advance.

 

wave1.JPG
wave2.JPG
wave3.JPG
wave4.JPG
wave5.JPG
wave6.JPG
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4 Replies
criley
Xilinx Employee
Xilinx Employee
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Registered: ‎08-16-2007

I believe rdlvl stage 1 always passes so it's important to review the results to find out which byte lane and/or bits are are failing. Then you'll want to determine if it's a Read or Write data error and then start probing the data and associated clock for signal integrity. You may also want to probe the command signals to ensure the timing is valid and within spec. 

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spman2
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Registered: ‎01-01-2013

Could you please explain more? How should I do that? Do I need more probes or altering example design?

 

Thanks

 

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spman2
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Registered: ‎01-01-2013

Hi,

 

It seems that the read data (dbg_rd_data, dbg_align_fd1_rd1_fd0_rd0_rdbg_iserdes_rd and dg_iserdes_fd signals) are constant during stage 1. (the value of these signals are shown in the first post)

What should I do? Please help me.

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vsrunga
Xilinx Employee
Xilinx Employee
8,194 Views
Registered: ‎07-11-2011

Hi,

 

Values will be constant for a byte, please find out the byte value and probe its DQS and DQ to compare its SI with other bytes

You can refer rdlvl_*   rtl file to have knowledge of various signals.

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