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Observer
Observer
468 Views
Registered: ‎06-25-2020

QDRII pin constrains

Hi,

I'm building a design containing 4 QDRII+. The clock configuration in xdc file is shown below

create_clock -period 10.181 [get_ports sys_clk_1_p]
create_clock -period 10.181 [get_ports sys_clk_2_p]
create_clock -period 10.181 [get_ports sys_clk_3_p]
create_clock -period 10.181 [get_ports sys_clk_4_p]

set_clock_groups -group [get_clocks sys_clk_1_p -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks sys_clk_2_p -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks sys_clk_3_p -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks sys_clk_4_p -include_generated_clocks] -asynchronous

set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports sys_clk_1_p]
set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports sys_clk_2_p]
set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports sys_clk_3_p]
set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports sys_clk_4_p]

set_property ODT RTT_48 [get_ports sys_clk_1_p]
set_property ODT RTT_48 [get_ports sys_clk_2_p]
set_property ODT RTT_48 [get_ports sys_clk_3_p]
set_property ODT RTT_48 [get_ports sys_clk_4_p]

set_property PACKAGE_PIN AV18 [get_ports sys_clk_1_p]
set_property PACKAGE_PIN BB36 [get_ports sys_clk_2_p]
set_property PACKAGE_PIN E38 [get_ports sys_clk_3_p]
set_property PACKAGE_PIN K18 [get_ports sys_clk_4_p]

However, the implementation failed at opt_design phase with the error below

[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port sys_clk_1_p has property DIFF_TERM_ADV set, but its I/O Standard, DIFF_SSTL15_DCI, does not support this property.
[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port sys_clk_2_p has property DIFF_TERM_ADV set, but its I/O Standard, DIFF_SSTL15_DCI, does not support this property.
[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port sys_clk_3_p has property DIFF_TERM_ADV set, but its I/O Standard, DIFF_SSTL15_DCI, does not support this property.
[DRC PORTPROP-6] I/O standard compatibility with attribute usage: Port sys_clk_4_p has property DIFF_TERM_ADV set, but its I/O Standard, DIFF_SSTL15_DCI, does not support this property.

Is there anyway to fix it?

Thanks.

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3 Replies
Xilinx Employee
Xilinx Employee
448 Views
Registered: ‎03-04-2018

Hello @nxthuan512 ,

 

Please use the DIFF_HSTL_I for sys_clk.  I checked it with example design on UltraSale.  Example design is described in the PG150, page.391, for QDRII.

https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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sys_clk.PNG
Moderator
Moderator
437 Views
Registered: ‎08-21-2007

Are these system clocks placed within the banks of the QDRII interface? It seems IO standard incompatibily here. You can move these pins or set up the compatible IO standard with QDRII. 

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Observer
Observer
416 Views
Registered: ‎06-25-2020

Hi,

Thank for your reply.

I found out the problem was DIFF_TERM ("TRUE").  In the example design, it is not set, which means "FALSE."

IBUFDS #
    (
     .DIFF_TERM    ("TRUE"),
     .IBUF_LOW_PWR ("FALSE")
     )
    u1_ibufg_sys_clk_4
      (
       .I  (sys_clk_4_p),
       .IB (sys_clk_4_n),
       .O  (sys_clk_4_i)
       );
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