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adieux
Contributor
Contributor
515 Views
Registered: ‎06-19-2017

Question with enabling Vref calibration

I am using Vivado 2018.3 and MIG 2.2 for DDR4. 

In PG150 "Read and Write VREF Calibration" section, it says Vref calibration is by default not enabled. However, by modifying the following lines in ddr4_0_ddr4.sv (under the MIG IP source):

 

parameter CAL_RD_VREF = "FULL",
parameter CAL_WR_VREF = "FULL",

 

and regenerating the IP (UG896 "Editing Subsystem IP" section), the vref calibration can be enabled. 

 

I did the above but my MIG calibration still skips the Vref calib. Any ideas? 

Vref.png

 

 

 

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kshimizu
Xilinx Employee
Xilinx Employee
435 Views
Registered: ‎03-04-2018

Hello @adieux ,

 

I’m not sure why the Vref is not conducted.  Please check the modified sour code again after generating IP.  I don’t have any evaluation boards at this time.

 

Also, I show the AR#57546, which describes how to modify the IP as a reference.

 

 

Best regards,

Kshimizu

 

Product Application Engineer Xilinx Technical Support

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adieux
Contributor
Contributor
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Registered: ‎06-19-2017

Thanks Kshimizu for your reply. 

In the PG-150 doc about MIG, it says this about why Vref Calibration is not done. 

Through characterization it has been determined that read and write VREF calibration are not required. 

The eye sizes found with the default read/write VREF settings are comparable to the eye sizes found 
with the calibrated read/write VREF values. 

So an alternative question can be: how to find out the Vref values after calibration? 

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