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Observer
Observer
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Registered: ‎08-26-2018

RLDRAM3 to VC707 through FMC

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Hello,

I have a VC707 evaluation board with Virtex 7 device on top, which I would like to interface with RLDRAM3 memory chip (MT44K32M36-125E). My initial plan is to design a custom PCB for the memory and connect it to the FPGA board through the FMC connector. I tried simulating a memory controller generated by the MIG tool and pin-wise everything seems to be in orde, i.e. FMC1 connector on VC707 has all the pins required by the MIG to make a valid memory interface. 

However, I am still quite new to memory interfaces and am not quite sure whether the physical distance between the FPGA and the DRAM memory chip on an FMC card (put as close to the connector as possible) is not too long, considering that the interface has to operate at 666 MHz. Could you please advise on this matter?

Also, in general, would it make sense to make FMC boards for other types of fast memories, such as DDR4 or QDR SRAM?

Thank you!

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Moderator
Moderator
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Registered: ‎11-28-2016

Hello @mstrdm,

The MIG IP was designed to interface with memories in short, point to point, topologies.  Going off the board to a FMC seems like a bad idea to me.  Overall I don't recommend this for any type of memory technology aside from HMC.  For the JEDEC governed technologies they don't make provisions for this and for SRAMs I've never seen it done.  If you're really stuck this may work as a solution but I wouldn't expect to operate at FMAX.

As far as trace lengths go the 7-Series guide UG586 doesn't have any specifics for this but I would absolutely reference UG583 that's used for UltraScale based memory IP.  Here in the RLD3 section starting on page 124 it goes over the various signal groups and gives recommendations for the max trace length for each segment.  Here's the table for the command/address/control bus signals:rldram3_cac_bus.PNG

 

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Moderator
Moderator
653 Views
Registered: ‎11-28-2016

Hello @mstrdm,

The MIG IP was designed to interface with memories in short, point to point, topologies.  Going off the board to a FMC seems like a bad idea to me.  Overall I don't recommend this for any type of memory technology aside from HMC.  For the JEDEC governed technologies they don't make provisions for this and for SRAMs I've never seen it done.  If you're really stuck this may work as a solution but I wouldn't expect to operate at FMAX.

As far as trace lengths go the 7-Series guide UG586 doesn't have any specifics for this but I would absolutely reference UG583 that's used for UltraScale based memory IP.  Here in the RLD3 section starting on page 124 it goes over the various signal groups and gives recommendations for the max trace length for each segment.  Here's the table for the command/address/control bus signals:rldram3_cac_bus.PNG

 

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Observer
Observer
631 Views
Registered: ‎08-26-2018

@ryana Thank you very much for the useful information!

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