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Adventurer
Adventurer
11,144 Views
Registered: ‎11-18-2013

Re: MCB - RZQ vs Memory Device Attributes for DDR3

Hello,

       Do the 7 series devices need RZQ and ZIO resistors to be placed externally for the FPGA? 6 series needed them but I don't see the MIG generate/assign pins for them. 

Thanks,

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Xilinx Employee
Xilinx Employee
11,139 Views
Registered: ‎07-11-2011

Hi,

 

@shashankm, I moved your question to MIG and made it new post.

 

With respect to termination and DCI concept of MCB and 7 series is different

For 7 series RZQ is needed at memory end and  VRP and VRN at FPGA end.

Please refer UG586 for all 7 series design guideliness and AR 51474 for termination details.

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf

 

http://www.xilinx.com/support/answers/51474.html

 

 

Hope this helps

 

Regards,

Vanitha

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Xilinx Employee
Xilinx Employee
11,134 Views
Registered: ‎08-01-2008

I think this is not right way to compare 6 -series and 7 series controller . It seems you need help on 7 series DDR3 controller.

Please follow the guideline for 7 series controller only. The document and guideline given for MCB is not useful for 7 series controller.
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
11,130 Views
Registered: ‎11-18-2013

Thanks for the reply Vanitha.

Please correct me on the following:

1) Artix series do not have HP banks and hence DCI is not supported (we are using a Artix device)

2) VRP and VRN are only needed when DCI is used (and VRP and VRN are not available in the Artix device). 

 

Regards,

 

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Xilinx Employee
Xilinx Employee
11,126 Views
Registered: ‎07-11-2011

Yes, Your understanding is correct!

If you do not find DCI option in MIG GUI for DQ pins it means the device you selected do not have HP banks and hence do not have DCI

You can use IN_TERM for such cases and do IBIS Simulations.

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Adventurer
Adventurer
11,123 Views
Registered: ‎11-18-2013

Thanks again.

I am using Vivado v2014.1 and what puzzles me is that even though the device that I have chosen does not have HP pins and correspondingly DCI is not possible; MIG does give an option to enable DCI. 

Is this a bug or am I doing something wrong?

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Xilinx Employee
Xilinx Employee
11,121 Views
Registered: ‎07-11-2011

Hi,

 

What is your FPGA device part number?

Can you have a snapshot here ?

 

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Adventurer
Adventurer
11,117 Views
Registered: ‎11-18-2013

Can I send it to you by email?

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Adventurer
Adventurer
11,115 Views
Registered: ‎11-18-2013

Here is the screenshot,

DCI_Issue_050614.png

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Xilinx Employee
Xilinx Employee
11,098 Views
Registered: ‎07-11-2011

Hi Shashank,

 

Hope you do not want to share the part number:)

I found a part that I can replicate the behaviour you stated, it looks something wrong for me.

I will go ahead and file CR.

My suggestion would be, if possible, not to use the Bank that shows as HP in MIG GUI, but select HR banks.

If in case your design needs the same bank(34) than you might need to take care of frequency, IOstandards and other things manually.

 

Hope this helps

 

Regards,

Vanitha

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Adventurer
Adventurer
8,574 Views
Registered: ‎11-18-2013

Hello Vanitha,

            It is not possible for us to change the bank now (PCB is complete) and we had earlier used the software to validate our DDR pin assignments. 

Is this a problem in the software or the device "secretly" has HP banks? 

May I ask you to please elaborate on If in case your design needs the same bank(34) than you might need to take care of frequency, IOstandards and other things manually.

 

Thanks,

 

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Xilinx Employee
Xilinx Employee
8,569 Views
Registered: ‎07-11-2011

Hi,

 

This is a problem with SW, device do not have HP banks, you will see the below error in implementation.

 

"ERROR: [Place 30-399] This design has IO with an IOSTANDARD of DIFF_SSTL15_T_DCI but the target device has no High Performance (HP) banks that support this IO standard."

 

I would suggest you to generate MIG for HR banks and copy the IOstandards in your actual design(Bank-34) XDC

If you undergo any hurdles please work with your FAE

 

 

Regards,

Vanitha

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