06-04-2014 11:40 PM
Do the 7 series devices need RZQ and ZIO resistors to be placed externally for the FPGA? 6 series needed them but I don't see the MIG generate/assign pins for them.
06-04-2014 11:45 PM - edited 06-04-2014 11:55 PM
@shashankm, I moved your question to MIG and made it new post.
With respect to termination and DCI concept of MCB and 7 series is different
For 7 series RZQ is needed at memory end and VRP and VRN at FPGA end.
Please refer UG586 for all 7 series design guideliness and AR 51474 for termination details.
Hope this helps
06-05-2014 12:23 AM
06-05-2014 01:54 AM
Thanks for the reply Vanitha.
Please correct me on the following:
1) Artix series do not have HP banks and hence DCI is not supported (we are using a Artix device)
2) VRP and VRN are only needed when DCI is used (and VRP and VRN are not available in the Artix device).
06-05-2014 02:00 AM - edited 06-05-2014 02:02 AM
Yes, Your understanding is correct!
If you do not find DCI option in MIG GUI for DQ pins it means the device you selected do not have HP banks and hence do not have DCI
You can use IN_TERM for such cases and do IBIS Simulations.
06-05-2014 02:14 AM
I am using Vivado v2014.1 and what puzzles me is that even though the device that I have chosen does not have HP pins and correspondingly DCI is not possible; MIG does give an option to enable DCI.
Is this a bug or am I doing something wrong?
06-05-2014 02:15 AM
What is your FPGA device part number?
Can you have a snapshot here ?
06-05-2014 10:23 PM
Hope you do not want to share the part number:)
I found a part that I can replicate the behaviour you stated, it looks something wrong for me.
I will go ahead and file CR.
My suggestion would be, if possible, not to use the Bank that shows as HP in MIG GUI, but select HR banks.
If in case your design needs the same bank(34) than you might need to take care of frequency, IOstandards and other things manually.
Hope this helps
06-06-2014 12:04 AM
It is not possible for us to change the bank now (PCB is complete) and we had earlier used the software to validate our DDR pin assignments.
Is this a problem in the software or the device "secretly" has HP banks?
May I ask you to please elaborate on If in case your design needs the same bank(34) than you might need to take care of frequency, IOstandards and other things manually.
06-06-2014 02:07 AM
This is a problem with SW, device do not have HP banks, you will see the below error in implementation.
"ERROR: [Place 30-399] This design has IO with an IOSTANDARD of DIFF_SSTL15_T_DCI but the target device has no High Performance (HP) banks that support this IO standard."
I would suggest you to generate MIG for HR banks and copy the IOstandards in your actual design(Bank-34) XDC
If you undergo any hurdles please work with your FAE