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8,490 Views
Registered: ‎08-22-2014

Re: MIG 3.5 can't implement on Spartan xc6slx45

Hi everyone

Even if this topic is a bit old, I just had the same issue and I found (I think) the cause in this topic :

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/LVDS-inputs-and-DDR2-DIFF-SSTL18-II-at-the-same-bank-error/td-p/165898

 

It seems that, in some cases, ISE disconnects the UCF file from the project, even if it does not show this separation...

This error message comes from ISE trying to place pins automatically at some random pins, and naturally, it goes wrong as random does not pick MCB dedicated pins...

 

It worked after removing the UCF from the project and adding it again just one sec latter.

 

Hope this helps

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Xilinx Employee
Xilinx Employee
8,485 Views
Registered: ‎07-11-2011

Re: MIG 3.5 can't implement on Spartan xc6slx45

Hi,

 

As Spartan-6 is old and no more ISE releases are planned if you have a work around then there is very little that we can help

 

If you are using Project Navigator then please follow the steps outined in below AR

http://www.xilinx.com/support/answers/37424.htm

 

If you face any issue using the flow and have a reproducible test case please upload it for any commets

 

 

Regards,

Vanitha

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