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taganrog
Explorer
Explorer
8,353 Views
Registered: ‎01-18-2011

Re: MIG User Interface back-to-back Write Timing

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HI!

 

PG150 at page 83:

"As shown in Figure 4-2, page 81, the maximum delay for a single write between the write data and the associated write command is TWO clock cycles. When issuing back-to-back write commands, there is NO maximum delay between the write data and the associated back-to-back write command, as shown in Figure 4-5."

 

Why the difference between back-to-back and single commands? Model with back-to-back write commands and one clock cycle delay for write data works properly.

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vsrunga
Xilinx Employee
Xilinx Employee
14,481 Views
Registered: ‎07-11-2011

Hi,

 

As it is back to back, I assume you are referring delay of 2 clocks for first write command versus data, if yes you can have it but for the subsequent commands app_wdf_data will follow previous data without out any gaps

 

Also visit below links for relavant discussions

http://forums.xilinx.com/t5/MIG-Memory-Interface-G​enerator/can-there-be-1-or-2-empty-cycle-delay-bet​ween-two-halves-of-BL8/m-p/364047#M4380

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Mig-User-Interface-Back-To-Back-Timing/td-p/503861

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-G​enerator/MIG-DDR3-questions-about-delays-and-buffe​rs-depthes/td-p/272216

 

-Vanitha

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vsrunga
Xilinx Employee
Xilinx Employee
8,347 Views
Registered: ‎07-11-2011

Hi,

 

In back to back command mode it is asumed that data is avaiable in the FIFO and hence the delay is not a big restriction.

For single write command you should make sure that the data associated with that specific address is supplied with in the time else existing data in the FIFO might be sent and there are chances to see misalignment

In any case you should be careful that data is sent first and then the command.

Note that controller will not validate which data belongs to which address and hence you need to take care that required data goes along with specified address

 

Hope this helps

 

-Vanitha

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Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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taganrog
Explorer
Explorer
8,263 Views
Registered: ‎01-18-2011

Thank you. I will ask otherwise. PG150 (november 19, 2014) at page 87 for non back-to-back write command:

"Write data is presented AFTER the corresponding write command, but should not exceed the limitation of TWO clock cycles."

Can I use this rule for the back-to-back write command?

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vsrunga
Xilinx Employee
Xilinx Employee
14,482 Views
Registered: ‎07-11-2011

Hi,

 

As it is back to back, I assume you are referring delay of 2 clocks for first write command versus data, if yes you can have it but for the subsequent commands app_wdf_data will follow previous data without out any gaps

 

Also visit below links for relavant discussions

http://forums.xilinx.com/t5/MIG-Memory-Interface-G​enerator/can-there-be-1-or-2-empty-cycle-delay-bet​ween-two-halves-of-BL8/m-p/364047#M4380

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Mig-User-Interface-Back-To-Back-Timing/td-p/503861

 

http://forums.xilinx.com/t5/MIG-Memory-Interface-G​enerator/MIG-DDR3-questions-about-delays-and-buffe​rs-depthes/td-p/272216

 

-Vanitha

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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