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taganrog
Explorer
Explorer
8,040 Views
Registered: ‎01-18-2011

Re: System Clock, PLL Location, and Constraints

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Can sysclock come from CCIO that locate in the same column, but not in the adjacent (or the same) bank?

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vsrunga
Xilinx Employee
Xilinx Employee
14,454 Views
Registered: ‎07-11-2011

Hi,

 

@taganrog please always start new threads for your new questions.

 

From UG586 -

The system clock input must be in the same column as the memory interface. The system clock input is recommended to be in the address/control bank, when possible

 

So Sys clock can come from any bank wih in the same column, if in case you see implementation errors you can use CLOCK DEDICATED ROUTE constraint, refer below link for more details

http://www.xilinx.com/support/answers/40603.html

 

Hope this helps

 

-Vanitha.

 

 

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vsrunga
Xilinx Employee
Xilinx Employee
14,455 Views
Registered: ‎07-11-2011

Hi,

 

@taganrog please always start new threads for your new questions.

 

From UG586 -

The system clock input must be in the same column as the memory interface. The system clock input is recommended to be in the address/control bank, when possible

 

So Sys clock can come from any bank wih in the same column, if in case you see implementation errors you can use CLOCK DEDICATED ROUTE constraint, refer below link for more details

http://www.xilinx.com/support/answers/40603.html

 

Hope this helps

 

-Vanitha.

 

 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

View solution in original post

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